Hyperlink documentation

I attach a training module about HyperLink

Please read it carefully.

Then post followup question on this form

Ran6332.14 Intro to Hyperlink.pptx

The PPT has one slide on interrupts.

This shows that the hyperlink interrupt is 111 and it outputs through CIC0 and CIC1 go to specific cores. What it doesn't answer is the following (posted earlier on

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/256609/898644.aspx#898644 where I was given an example).

This references the following chain of interrupt-related numbers: 111 : 64 : 22 : 4

I understand 111 is the hyperlink input to CIC0 and this is being explicitly mapped to channel 64. Where does 64 come from?

I understand that host event 22 is mapped in the INTMUX registers to CPU interrupt 4. Where does 22 come from?

Also, how do you get from channel 64 to host event 22? Where is this documented?

I have also been pointed towards file:///F:/3L%20Documents/TI/C6678/Interrupts/Configuring%20Interrupts%20on%20Keystone%20Devices%20-%20Texas%20Instruments%20Embedded%20Processors%20Wiki.htm

This contains the following:

/* Note that hyplnk_EXAMPLE_INTC_OUTPUT = 32 + (11 * CoreNumber) = 43 for Core0*/

Either Core 0 gives a CoreNumber of 1 or "Core0" is a typo for Core 1. In either case, why is this example using 43 (or possibly 32) where the other example uses 22?

There are so many levels of infirection ands magic numbers (probably scatterd over several documents) that I find it impossible to follow what's going on.

Regards,

Peter

Look at the attached file6521.I will try to answer your questions.docx

Thanks for your document.

All these documents remind me of an old game on the PDP11 where there was a highly significant distinction between "Maze of twisty little passages", "Little maze of twisty passages", "Twisty little maze of passages" etc. All so similar that it's easy (deliberate) to become completely confused. So it is with "Secondary Events", "Reserved Secondary Events", etc and the numerous interrupt controllers. It would have been so much clearer if the diagram showed all of the available interrupt causes on the left, with the top set (the primary ones) going directly to the (whatever they're called) event handlers and some (the secondary ones) going through the CICs essentially to become new primary causes. The diagram you copy is just far too noisy. Something this intricate surely needs very carefully-written documentation that makes the minimum number of assumptions and leaves no room for confusion. I think it's telling that you need side documents to explain how these things work; my conclusion is that the base document is inadequate.

I have managed to work out how to connect up the chain of numbers, but I am still in the dark about your comment "it looks like any interrupt to the hyperLink will result in a packet interrupt to the other side". Could you please explain EXPLICITLY how to generate this interrupt that results in a packet interrupt to the other side?

I have manage to get my code working by setting bits in B's Interrupt Pending/Set Register via A's Remote Interrupt Pending/Set Register. This doesn't send any interrupt packet, but it seems to work and has the advantage of being almost trivial to do.

Regards,

Peter

I am happy that you made it work.

Would you be kind enough to take your project (or projects), strip out any proprietary information and put it on e2e as an example? I assume that if you had difficulties, others will encounter the same issue in the future.

Best regards

Ran

I shall post what I can, although I do not use CSL or BIOS as I find it far easier and clearer to use the registers directly (it also generates a fraction of the code).

You did not answer my question: "Could you please explain EXPLICITLY how to generate this interrupt that results in a packet interrupt to the other side?"

Regards,

Peter

As promised, here is some code I have abstracted from my system to show how I am using the hpyerlink to transfer data from one core to another.

I hope it is helpful.