C6674 DDR3 chip select question

Piet,

I assume that it is driven high but this is not clearly defined.  A board design only having a single rank will not have DDRCE1# so this becomes a don't care.  Why do you ask?

Tom

I have a board where the DDR chip select line is wrongly connected to #CS1 instead of #CS0.

All other DDR lines are only connected to the chip select zero versions (e.g. CKE, ODT etc)

I can make a modification to short #CS0 and #CS1 to get a connection to #CS0 of the DSP.

If #CS1 is tri-stated it could work, but if #CS1 is driven high, then it will conflict with #CS0

If SDCFG.EBANK is set to 0 then DDRCE1 is always driven high except during initialization, refresh, self refresh, power-down and deep power-down commands. These commands are executed simultaneously on both banks and the DDRCE1 will be driven low as part of the command.

Regards, Bill 

Hi Bill

Does the fact that DDRCE1 is low during initialization, mean that Partial Automatic Levelling should work on our hardware, even if DDRCE1 is connected to the DDR memories instead of DDRCE0 ?

Our Partial Automatic Levelling times out for all three trainings.

Hi Piet,

If you are attempting to use the board with no memory on DDRCE0 and DDRCE1 connected to a single rank you are using it in an unsupported mode. I'm not sure how it will level with this type of connection but I do know that you won't be able to easily use the memory if leveling completes. When ebank is set to 1 the SOC is expecting two banks of memory and the chip select is part of the address mapping. That mapping from the MSB of the address to the LSB is as follows.

Row address, chip select, bank address, column address. 

As you can see your memory map would become a checkerboard of unusable blocks. I think you need to fix the issue with your board before you continue.

Regards, Bill

Hi Bill

We have a single rank of 4x 16-bit memories connected to all the control lines associated with DDRCE0, but by mistake connected the chip select line of the memories to DDRCE instead of DDRCE0.

One option was to short CE0 and CE1, but from the reply above I realize that it won;t work because (as you said) DDRCE1 is not tri-stated when EBANK=0 but is driven high.

My question is if the training performed in Partial Automatic Levelling should work with our incorrect DDR chip select connection or not?
Your comment that both DDRCEx lines are driven low during initialization, made me wonder if the training should actually work?

We get training time-out during our Partial Automatic Levelling.

Regards

Piet

Hi Tom

I think this confirms why our levelling times out.

We should be able to fix the DDRCE pin swap and hopefully the rest will then work.

Thanks for you and Bill's detailed answers.

Kind regards

Piet

Piet,

You will need to validate all of the routing rules have been met in your new layout.  Has this been done?  Please see the thread referenced below for the step-by-step process.

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/245304.aspx

Tom

Hi Tom

I'll check this.

Thanks, Piet