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DM368 IBIS Model for DDR2

g.f.
Guru 15520 points

Hi,

I have a question about DM368 IBIS model.

I'm trying to simulate DDR2 interface.
IBIS model which we can get from TI DM368 web site,
there are MODEL "BSSTL18TCSCGPBFZ" for DDR2 I/F.

I have a question about this Model.
In IBIS, following description are written:
==================================================
|SR0 IS SLEW RATE CONTROL BIT WHICH DECIDES THE MODE OF OPERATION
|T0 AND T1 ARE TERMINATION BITS WHICH CAUSE NO,HALF,FULL TERMINATION
|NO TERMINATION WHEN T0=0 WHEN T1=0
|HALF TERMINATION WHEN T0=1 WHEN T1=0
|FULL TERMINATION WHEN T0=0 WHEN T1=1
|SSTL RECIEVER MODE WHEN CMOSEN = 0
|LVCMOS RECIEVER MODE WHEN CMOSEN = 1
===================================================

1.Is SR0 supported in DM368?
  I checked DDR2 UG but there was no appropriated register for SR0,
  so I guess it's not supported.

2.It looks we can choose "NO", "HALF", "FULL" Termination,
  but which from DDR2 register we can select the termination?
  Is it DDRDRIVE[1:0] which is bit field of SDCR register?
  My understanding is FULL TERMINATION = normal strength, HALF TERMINATION = weak strength,
  and there are no setting for "NO TERMINATION".
  Am I right?

3.There are two reciever mode, SSTL and LVCMOS.
  My uderstanding is only SSTL are supported in DDR2
  so you need to choose SSTL MODE.
  Am I right?

best regards,
g.f.

DM368 IBIS Model for DDR2

  • 0
    TI__Genius 9775 points

    Hello,

    What is the main purpose of your IBIS simulations?  Please note that the DDR2 interface on DM368 is supported only by following the DDR2 routing requirements in the data sheet.  By following these requirements, you no longer need to run IBIS simulations.  However, you must ensure you follow all of the presented routing rules.

    Thanks.

  • 0 in reply to Ivan Garcia
    Guru 15520 points

    Hi Ivan,

    Thank you for the resposne.

    Actually our customer are having a read access problem right know,
    which I posted to the following E2E:
    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/100/t/259277.aspx

    They are trying to simulate the timing with IBIS,
    so they are asking which Model are appropriate.

    Since the contents I posted this time are heard not only in this time,
    please let me know.

    best regard,
    g.f.

  • 0 in reply to g.f.
    TI__Genius 9775 points

    G.F.,

    The most likely issue in this case is either the improper setup of the EMIF (i.e. EMIF register timings are not programmed according to the type of memory connected on the board) or the use of improper termination which does not follow the data sheet.

    Can you check vs the EVM as well as the data sheet block diagram schematic?  http://support.spectrumdigital.com/boards/evmdm365/revf/ 

    Furthermore, could you check that the EMIF registers are properly programmed?  I.e., CAS Latency, refresh periods, etc.

    Thanks.

  • 0 in reply to Ivan Garcia
    Guru 15520 points

    Hi Ivan,

    Thank you for the response.

    I understood.
    I have memory data sheet and customer's setup of EMIF register,
    so I will check either EMIF registers are setup correctly or not.

    And also I will check the schematics.

    By the way, I uderstood that IBIS is no longer need it,
    but I would like to know the answer of my question which I posted first,
    so could you please give me the information.

    best regards,
    g.f.