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OMAP L138 silicon errata SPRZ301F advisory 2.1.1 question regarding workarounds

Rob van de Voort
Intellectual 630 points
Other Parts Discussed in Thread: OMAP-L138

I have a question regarding the Silicon Errata of the OMAP L138 [ SPRZ301F ]
Advisory 2.1.1 DMA Access to L2 RAM can stall …. Etc.

I do not yet understand the workaround in this advisory,
the following questions arose when trying to implement the workarounds.

Assumption:
What I think I should do to avoid the issue in advisory 2.1.1 is apply priority values which
make sure the following statements hold ( are true ). 

Statement 1: CPUARBU[ PRI ] < 7  ( 6, 5 … 1, 0 )
Statement 2: CPUARBU[ PRI ] =! IDMA1_COUNT[ PRI ]
Statement 3: CPUARBU[ PRI ] =! MSTPRI1 [ * ]
Statement 4: CPUARBU[ PRI ] =! MSTPRI2 [ * ]
Statement 5: CPUARBU[ PRI ] =! MSTPRI0 [ * ]

Question1:
Is this the correct assumption about the priorities or do I miss something?

* = all non-reserved fields in this register

Question2:
Does MSTPRI0 have an effect on this issue?
    What about the SATA port and the uPP port?
    What about the DSP_CFG and DSP_MDMA ports?

Definitions used:
0 is highest priority, 7 is lowest priority value as stated in datasheet of OMAP L138 and PRI register field.
notation REGISTER_NAME[ FIELD ] to show a specific field in the register

Hope you can answer this question and make the workaround implementation clear to me,

Regards Rob van de Voort

  • 0
    Intellectual 630 points

    For completeness of the question I used the following references:

    SPRUH77A - for the MSTPRI register definition section 11.5.9
    SPRUFKA   - for other registers like CPUARBU section 6.3.1 and IDMA Channel 1 Count Register (IDMA1_COUNT) section 5.4.9
     

    A TI employee contacted me, and forwarded my question, patiently waiting for an answer 

     

  • 0 in reply to Rob van de Voort
    TI__Expert 7470 points

    Hi Rob,

    Your understanding is correct. Essentially CPU priority should be <7 and not equal to the DMA priorities.

    Any peripheral that has access DMA SDMA should be taken into account. As can be seen from Table 4-1. OMAP-L138 Applications Processor System Interconnect Matrix in the TRM (spru77a), SATA, uPP etc have access to SDMA, but from a practical usage point of view most will not access L2 RAM. If they do in your system, you will have to account for their priorities in MSTPRI0 also. DSP_CFG and DSP_MDMA do have access to SDMA.

    Hope this clarifies your question.

    Regards,

    Sunil Kamath

  • 0 in reply to Sunil Kamath
    TI__Expert 7470 points

    Sunil Kamath said:
    DSP_CFG and DSP_MDMA do have access to SDMA

    Meant to say "... DSP_CFG and DSP_MDMA do NOT have access to SDMA"

    -Sunil