AM335x RGMII Ethernet PHY

I'm not aware of this PHY being used before on AM335x, but I did not find anything that would preclude its use after a quick review of the product datasheet.

It's important to note that this PHY does not appear to support internal delay mode as a strap option. Without internal delay as a strap option, it will not be (practically) possible to boot from a Gig connection. Booting from 10/100 connections will not be affected.

Edit: Booting from 10/100/1000 with this PHY will not be possible as it does not have the ability to strap internal delay mode.

Hi -DK-,

Our customer uses VSC8211 with AM335x of silicon revision 2.1.

Is the internal delay mode by PHY required for the rev2.x devices?

The rev2.x devices should support internal delay mode since the internal delay mode issue (Advisory 1.0.10 in Silicon Errata) has been fixed.

Best regards,

Daisuke

Internal Delay mode is not supported on any version of AM335x. It has been deprecated as a feature.

The issue described by Advisory 1.0.10 is that the SoC was enabling Internal Delay (an unsupported feature) by default. Subsequent revisions of the silicon no longer have Internal Delay enabled by default.

So the answer to your question is yes, from a practical perspective, customers must choose a PHY that supports Internal Delay mode. Furthermore, they must choose a PHY that supports externally-strapped Internal Delay if they wish to boot from the relevant Ethernet port. In all cases, TI recommends a complete timing analysis of the interface to ensure that timing can be met on both TX and RX.

Hi -DK-,

Thank you for your reply.

I checked the VSC8211 datasheet. VSC8211 seems to support the internal delay mode by registers configuration or externally-strapped configuration.

"Bits 23.11:10 specify the amount of clock delay added to the TX_CLK line inside the VSC8211 when using an RGMII or RTBI interface."

"Bits 23.9:8 specify the amount of clock delay added to the RX_CLK line inside the VSC8211 when using an RGMII or RTBI interface."

"The default values of these bits are specified by the RGMII Skew bits in the CMODE hardware configuration."

Can you guess that these indicate the internal delay mode required by AM335x?

I will suggest to the customer using a PHY supporting the internal delay mode if VSC8211 does not support it.

Best regards,

Daisuke

Hi -DK-,

Thank you for your reply.

I checked the VSC8211 datasheet. VSC8211 seems to support the internal delay mode by registers configuration or externally-strapped configuration.

"Bits 23.11:10 specify the amount of clock delay added to the TX_CLK line inside the VSC8211 when using an RGMII or RTBI interface."

"Bits 23.9:8 specify the amount of clock delay added to the RX_CLK line inside the VSC8211 when using an RGMII or RTBI interface."

"The default values of these bits are specified by the RGMII Skew bits in the CMODE hardware configuration."

Can you guess that these indicate the internal delay mode required by AM335x?

I will suggest to the customer using a PHY supporting the internal delay mode if VSC8211 does not support it.

Best regards,

Daisuke

From what you posted here, it appears that this PHY does support Internal Delay via both software and hardware (assuming that CMODE5 refers to a series of pins on the device). Because each board design is different, this particular solution would need to be "tuned" to determine the ideal delay. Typically, the inserted delay needs to be ~1.8ns for designs that have length-matched transmit/receive:data traces, so I'd start with '00' (2ns) and verify sufficient timing via direct observation with a scope.

Hi -DK-,

Thank you for your reply.

Best regards,

Daisuke

Hi -DK-,

I have an additional question.

I want to know whether VSC8211 can be used for EMAC boot.

Please see the 26.1.8.4.1 on TRM(SPRUH73L). In Device Initialization, the ROM code assumes that the Ethernet PHY with the lowest MDIO address (0-31) is connected to CPGMAC port 1.

The registers in the address 16-31 are "Vendor Specific" which is specified in the IEEE802.3u clause 22. Does the ROM code not configure these registers?

Best regards,

Daisuke

I just want to clarify some points in this discussion.

Each Ethernet PHY attached to the MDIO interface has a unique MDIO address from 0 to 31, that identifies it from other Ethernet PHYs connected to the same MDIO interface.

The ROM code begins looking for a PHY attached to the MDIO interface by searching from the lowest MDIO address to the highest MDIO address.  Once it finds a PHY, it assumes this PHY is attached to CPGMAC port 1 and uses this combination to boot from Ethernet.  If the product has more than one Ethernet PHY attached to MDIO interface the one with the lowest MDIO address must be the one connected to CPGMAC port 1.

The PHY has registers as defined in IEEE 802.3 clause 22 and these registers have register addresses from 0 to 31, where register addresses 16 to 31 are vendor specific.

Since the ROM code doesn’t know what type of PHY is connected, it only configures the registers common to all PHYs.  This is the reason IO delays in the PHY must be configured via external pins before the ROM code executes the Ethernet boot code.

Regards,
Paul

Hi -DK- and Paul,

Thank you for your reply.

Best regards,

Daisuke