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PCI configuration in C6455

yosio ando
Prodigy 110 points

I have created a board with two C6455.
I'm connected by PCI between the C6455.
Let me be the one Master.
fail to be carried out in accordance with the PCI Configuration sprue60 9.1.1.
It is set in the following manner, but how will it wrong.

----------------------------------
#define PCIMCFGDAT ((unsigned int*)0x02C00300)
#define PCIMCFGADR ((unsigned int*)0x02C00304)
#define PCIMCFGCMD ((unsigned int*)0x02C00308)


busno = 0;
devno = 0;
funcno = 0;
addr = 0;

bno_bit = (busno << 16);
dno_bit = (devno << 11);
fno_bit = (funcno << 8);
adr_bit = (addr & 0xfc);

/* Check READY bit */
while(1)
{
if(*PCIMCFGCMD & 0x80000000)
{
break;
}
}

*PCIMCFGDAT = 0xB000104C;
*PCIMCFGADR = 0x80000000 | bno_bit | dno_bit | fno_bit | adr_bit;
*PCIMCFGCMD = 0x000000F1;

/* Check READY bit */
while(1)
{
if(*PCIMCFGCMD & 0x80000000)
{
break;
}
}
----------------------------------

The problem occurs in Check READY bit of the second.
There seems to be no end bit.

Thank you everyone.

  • 0
    TI__Genius 12065 points

    First, if you would like to issue Configuration Write Transaction, the RD_WR field in PCIMCFGCMD register should be set to 0x0 instead of 0x1, is it correct?

    *PCIMCFGCMD = 0x000000F1;  -> *PCIMCFGCMD = 0x000000F0;

    And how do you assert PIDSEL input to the slave please? Based on the PCI protocol specification, slave will respond to the Configuration Transactions when IDSEL is asserted. And IDSEL signal could be connected to one of the upper 21 address lines, which are not used in a configuration access. Then IDSEL could be asserted during address phase. But it is dependent on system implementation. 

    Please see the details in the PCI protocol specification such as 3.2.2.3.4 "Selection of a Device's Configuration Space" and 3.2.2.3.5 "System Generation of IDSEL" in PCI specification Rev 2.3.

  • 0 in reply to Steven Ji
    Prodigy 110 points

    Thank you Steven.

    I tried to implement both Read / Write settings PCIMCFGCMD.
    But both were useless.

    I have a connection for PIDSEL.
    However, there seems to be a problem before it.
    It was found that we have confirmed the signal of PIN, PREQ is not out.
    Settings to give the PREQ seems missing.

    I want you to tell me if there is an idea.
    Thanks in advance.

  • 0 in reply to yosio ando
    TI__Genius 12065 points

    On the PCI Master device, do you set 0x1 in "BUS_MS" bit in PCICSR or PCICSRMIR register please?

    It enables the PCI bus master capability of the device. 

  • 0 in reply to Steven Ji
    Prodigy 110 points

    Thank you Steven.
    It was confirmed that the READY bit PCIMCFGCMD becomes both 1 Write / Read by setting to 1 "BUS_MS" bit of PCICSRMIR.
    It was also confirmed that the value of PCIBAR0MIR changes by writing to 0x10.

    A new issue came out.
    I have created in the following way: the address to be specified in the PCIMCFGADR.
    bno_bit = (busno << 16);
    dno_bit = (devno << 11);
    fno_bit = (funcno << 8);
    adr_bit = (addr & 0xfc);
    0x80000000 | bno_bit | dno_bit | fno_bit | adr_bit;

    Try setting by changing the value of devno and busno.
    And is set to PCI Configuration of Master DSP all.
    Value of PCI Configuration Mirror Register of Slave DSP does not change.

    It was detected in the Device with the following settings to try.
    Detection is the reading of the VendorID.
    busno = 0
    0 <= devno <= 31
    0 <= funcno <= 7
    In advance, I set the 0xB000104D to PCIVENDEVMIR of Master DSP.
    I set the 0xB000104C to PCIVENDEVMIR of Slave DSP.
    Then, 0xB000104D was read in funcno devno of all of all.

    I wonder there is an error in how to specify the address.

    Thanks in advance.

  • 0 in reply to yosio ando
    TI__Genius 12065 points

    How does the IDSEL is connected in your design please? And Is the IDSEL asserted to PCIe Slave during Address phase please?

    It will be good to check the signal output/input sequences in  your design refering to section 9.1.2 in C6455 PCI user guide.

    And PCI standard specification has diagram to show the signal sequence as well for Configuration Read, such as Figure 3-4 in Rev2.3, which you could refer to:

  • 0 in reply to Steven Ji
    Prodigy 110 points

    Thank you Steven.
    It was possible to confirm the Type0 Address Configuration of HW, rewriting the BAR0 ~ 5 the Slave.

    Has not yet performed PCI communication using EDMA3, this thread ends.
    I'm very grateful. Thank you.