We are currently developing a Digital Video Encoder based on DM365 and are facing an issue with the PLL configuration. We are following the datasheet of TMS320DM365 Digital Media System-on-Chip for configuring the PLL as per our requirements(Attached please find the same). The crystal frequency is 24 Mhz and the PLL has been configured to provide 216 Mhz to the ARM core. This has been done as instructed in table 3-6 on page 61 of the attached document. With this configuration, we are getting a 26.4 Mhz SYSCLK9 output frequency(CLKOUT2). This goes directly into the video encoder chip. But the encoder chip needs at-least 27Mhz input frequency to work properly.
What are the possible methods to obtain a 27Mhz SYSCLK9 frequency? How far can we increase the PLL output to achieve this? Or what is the maximum output frequency possible for each of the PLLs?
