C674x UHPI HAS Used issue

Hi Daisuke,

As per the C6746 TRM UHPI_HAS pin has no host connection function we always connect this pin to logic high.

Figure 20-2 Example of Host =processor signal connections shows that UHPI_HAS pin is tied to logic High

Figure 21-0 HPI block Diagram shows that UHPI_HAS pin is tied to logic High

Figure

Regards

Antony

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Hi Antony,

Thank you for your reply.

For UHPI_HAS pin, the datasheet describes the timing characteristics.

TMS320C6746 Fixed- and Floating-Point DSP (Rev. D)
http://www.ti.com/lit/ds/sprs591d/sprs591d.pdf
Figure 5-54. UHPI Read Timing (HAS Used) [Page 201]
Figure 5-56. UHPI Write Timing (HAS Used) [Page 203]

I have already asked how to use the UHPI_HAS pin.

http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/249637.aspx

Best regards,

Daisuke

Hi Antony,

Can you make it clear whether or not C674x supports the UHPI_HAS pin?

Best regards,

Daisuke

Hi Daisuke,

Sorry for the delay in responding to your posts.

I suppose the customer has already made sure that the timing requirements are met. Can they share the high-level connections between the HPI and the GPMC and relevant timing for GPMC switching characteristics?

Rgds,

Sunil

Hi Sunil,

Thank you for your reply.
Sorry for my late reply.

The high-level connections between the HPI and the GPMC are as follows:

For the HPID write access, the conditions are as follows:

 - HPIC: 0x00000000

 - HPIA: 0xC0040000

 - HPID (without autoincrement): 0xFFFFFFFF

When GPMC is used, the access of 2nd half-word fails. The trace of the access is as follows:

When GPMC is used and the access of 2nd half-word is performed two times, the access can succeed.
To succeed, the first access in two times writes 0x0000 (UHPI_HR/W is Low). The trace of the access is as follows:

When GPIO is used and UHPI_HAS during UHPI_HSTROBE inactive cycle (UHPI_HCS is High) is not kept High, the access of 2nd half-word fails.
The trace of the access is as follows:

When GPIO is used and UHPI_HAS during UHPI_HSTROBE inactive cycle (UHPI_HCS is Low) is not kept High, the access of 2nd half-word fails.
The trace of the access is as follows:

When GPIO is used and UHPI_HAS during UHPI_HSTROBE inactive cycle is kept High, the access succeeds.
The trace of the access is as follows:

Best regards,

Daisuke

Hi Daisuke,

Lot of information to digest here before I can respond. Please give me some time for this.

Rgds,

Sunil

Hi Sunil,

Thank you for your reply.

For correct operation, if UHPI_HAS during UHPI_HSTROBE inactive cycle must be kept High, for UHPI_HAS the signal which GPMC_ADVn_ALE and GPMC_CSn[0] were passed through an external OR-gate will be used.

Best regards,

Daisuke

Hi Sunil,

Are there the progress? Could you let me know the current status?

Best regards,

Daisuke

Hi Sunil,

Daisuke Maeda said:

For correct operation, must UHPI_HAS during UHPI_HSTROBE inactive cycle be kept High?

Our customer wants this answer soon. Your prompt reply would be appreciated.

Best regards,

Daisuke

Hi Sunil,

Thank you for your reply.

The HAS signal will be external-gated by HCS.

The HR/W signal setup time before the UHPI_HAS Low is needed least 5ns. It seems to be met.

Best regards,

Daisuke