can't change EMIF's read setup value in C6678

Hi Feng,

The OE is a low true output. It's difficult to make out the details of the picture that you sent but it appears that the cursor is bracketing two EMIF accesses. You have circled the OE going high between the first access and the second access. Note that there is no guarantee that the CS will go high between two accesses. If accesses are close together the CS may stay low until all accesses are complete.

Regards, Bill

Thanks Bill,

I had found my fault that I forgot to use the function memcopy to set the value into the EMIF config registers.

But after I did that, I met other questions.

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1. I captured the OE signal and the results howed me that the OE went high after the read setup. See the picture below

In the picture above, you can see when the RnW signal goes high (it means that it's in reading) the OE

signal will go low and high and then low again. So I think the OE goes opposite to the description in datasheet.

And the more details I describe in the picture above will show you what I think.

.

2. I meet another big question.

The problem was that the delay between two EMIF reading access was too high, almost 24 EMIF cycles!!!

And the problem was completely like this guy's decription in http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/192245.aspx. I had got the same EMIF reading timing with this guy's. But in the posts of that thread, I can't find the final solution.

But:

I didn't use the EDMA to read the EMIF, just used the code below

while(1)

{

           *( DDR3_test_address++) = * DSP_EMIF_CE0;

           //My ddr3's data width is 32bits and EMIF's data width is 16bits, so this code must read two times

}

Maybe when I used the EDMA, I could get a better result. Could you show me some examples of EMIF EDMA to DDR3?

.

So please help me!

Yours,

Feng

Hi Feng,

Your image is showing two separate accesses to the EMIF interface. Do you have the width set up as 16bits or 8bits? I suspect that you are accessing the EMIF with a read type that is of a greater width then your EMIF bus width. When you attempt to do the read, the EMIF interface will automatically detect that it needs to access memory twice to fulfill the entire read. For example if your software attempts to read a 32bit value and you have your EMIF bus configured as 16bits, the EMIF interface will force two reads of 16bits each.  Your image shows the CS going low followed by the OE going low for the first read, the OE going high between reads and then the OE going low again for the second read. When the OE is high, no read is taking place.

The thread that you referenced has some detailed information concerning increasing the throughput on the EMIF interface. Note that the EMIF was not intended to be a high speed interface for streaming data. If you need to stream data into the part at high speeds then you may want to consider using the SRIO interface. On the second page of the reference thread the following post describes how to configure the EMIF for the fastest possible throughput. 

Even though this is an older thread, I wanted to post some recent information.

In some cases of use of the EMIF16, we have found that an unused internal feature can cause unintended delays between some EMIF16 accesses. This feature can be disabled by setting the msb of 0x20C00008 to 1. I recommend setting this in all cases for the C6678, and placing it near the top of your main() function.

*(Uint32*)0x20C00008 |= 0x80000000;  // Disable unused internal EMIF feature

Regards, Bill

Thanks Bill!

.

Bill Taboada said:

For example if your software attempts to read a 32bit value and you have your EMIF bus configured as 16bits, the EMIF interface will force two reads of 16bits each.  Your image shows the CS going low followed by the OE going low for the first read, the OE going high between reads and then the OE going low again for the second read. When the OE is high, no read is taking place.

Very impressive explain!!! I'll test again tomorrow and give you the feedback.

.

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Bill Taboada said:

In some cases of use of the EMIF16, we have found that an unused internal feature can cause unintended delays between some EMIF16 accesses. This feature can be disabled by setting the msb of 0x20C00008 to 1. I recommend setting this in all cases for the C6678, and placing it near the top of your main() function.

*(Uint32*)0x20C00008 |= 0x80000000;  // Disable unused internal EMIF feature

I had used this code in the top of main() but I didn't see any improvement. I'll try again.

.

.

Yours,

Feng

Hi Bill,

In the EMIF manual we have that it may be possible that the EMICE signal does not become inactive if there's another access of the same type to the same chip select space, how this can be achieved?

Because based on what we see in the forum, no one was able to do that, we always have a big delay (like the 24 EMIF cycles mentioned previously) between two reads. Do you have a test case where this problem was solved?

Thanks in advance.

J

Hi J,

The EMIF interface determines whether there is another access pending before determining if the CE becomes inactive. This can't be controlled by the user. Your design would have to be able to handle accesses which are separated by an inactive CE and accesses where the CE remains low. 

As I mentioned previously, the EMIF interface was not designed for streaming data. I'll contact the group that was investigating this previously and see if they have any comment.

Regards, Bill

Bill,

.

I just want to transfer 50KBytes in 1.3ms (almost 39MB/s) from FPGA to C6678 through EMIF interface. Can I get this perfermance? And how can I get?

.

Yours,

Feng

Hi all

Feng,you choose ( | (2 << 7)      /* readStrobe  48 ns */ \ ).

Are there any reason for this decision?

When I  transfer data from FPGA to C6678 through EMIF16 interface, C6678 some time need to wait. when I choose read Strobe less than 7, C6678 can not see signal wait, that FPGA send to C6678!!

I need to decrease read strobe to increase the read speed.

Thanks for any replies!