ROM SPI Boot problem

Sunghwan Kang

Prodigy 170 points

Hello.

My EVM is TMDSEVM6657LS

I tested been the boot option for ROM SPI Boot (No EEPROM, No IBL, Just direct to ROM SPI Boot).

But, now I have problem.

Below step is my test procedure.

Please check, and where do I fix it.

1. I use the executable file for my test

- mcsdk_2_01_01_04\tools\boot_loader\examples\i2c\nor\evmc6657l\bin\i2cnorboot_evm6657l.out

- This example software just print out to UART:

"NOR Boot Over I2C Example Version 01.00.00.00"
"Booting Hello World image from NOR flash via IBL over I2C 0x51 ..."

2. I make the batch file

- spiboot.bat

     hex6x spiboot.rmd
     bconvert64x -le spiboot.btbl spiboot.le.btbl
    b2i2c spiboot.le.btbl spiboot.le.btbl.i2c b2ccs
    spiboot.le.btbl.i2c spiboot.le.btbl.i2c.ccs
    romparse spiRom.map.pp
    ccs2bin i2crom.ccs spirom_le.bin
    ccs2bin -swap i2crom.ccs spirom_le.swap.bin
    rm i2crom.ccs spiboot.btbl spiboot.le.btbl spiboot.le.btbl.i2c spiboot.le.btbl.i2c.ccs

3. spiboot.rmd: I copy the C:\ti\mcsdk_2_01_01_04\tools\boot_loader\ibl\src\make\ibl_c665x\ibl.rmd and modified.

- spiboot.rmd

   spiboot.out
-a
   -boot
   -e _c_int00
-order L
   ROMS
   {
     ROM1: org = 0x0400, length = 0x20000, memwidth = 32, romwidth = 32
      files = { spiboot.btbl }
   }

4. spiRom.map.pp: I copy the C:\ti\mcsdk_2_01_01_04\tools\boot_loader\ibl\src\make\ibl_c665x\spiRom.map.pp and modified.

- spiRom.map.pp

    section
   {
    param_index    = 0
    boot_mode      = 50
sw_pll_prediv = 0
sw_pll_mult    = 0
sw_pll_postdiv = 0
sw_pll_flags   = 0
   options        = 1
core_freq_mhz = 800
    bus_freq_mhz     = 1
bus_freq_khz     = 0
addr_width   = 24
n_pins       = 5
mode         = 1
csel         = 2
    exe_file = "spiboot.le.btbl.i2c.ccs"
    }

   layout
   {
   dev_addr     = 0x400
   dev_addr_ext = 0
   file_align   = 0x80
   exe_file    = "spiboot.le.btbl.i2c.ccs"
   pad_file_id = 1
   exe_file    = ""
   pad_file_id = 1
   }

    pad
{
pad_file_id = 1
    dev_addr     = 0x500
dev_addr_ext = 0
len          = 0x300
    }

5. I excuted the spiboot.bat and have not error message.

6. In CCS, I load the NOR Writer at CCS Debug, and load the image "spirom_le.swap.bin" to memory index 0x80000000

7. I run the NOR Writer and successfuly loaded the image "spirom_le.swap.bin" to EVM

8. I change the DIP Switch for booting from ROM SPI and re-boot.

ROM SPI Boot: DIP SW3 (off, on, off, off, on, on, on, on) SW5 (on, on, off, on, on, on, on, on)

9. Terminal do not show message.

Above procedure, Where do I change?

Please help me.

over 11 years ago

0 ilay nissim over 11 years ago

Intellectual 530 points

There are 2 external pins in the evm switch which determines from which offset (0x00, 0x100...) the RBL will try to read from the spi

try to play with this 2 pins, maybe there are set so the RBL will try to read from offset 0x000 instead of 0x400 which you are setting

i think in sprugy5b table 3-29 section 3.6 this is called parameter table index.

i think you have to play with the 2 left dip switch in switch 4

the default for spi

sw3 sw4 sw5 sw6

(off, on, off, off)

(on, on, on, on)

(on, on, off, on)

(on, on, on, on)

try to change SW4 to

SW4(on, off, on, on),

SW4(off, off, on, on),

SW4(off, on, on, on),

have a look here http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/266165.aspx for more details

0 Sunghwan Kang over 11 years ago in reply to ilay nissim

Prodigy 170 points

Hello, ilay.

I already tested the example ROM Ethernet Boot.

In that test, I used the same ".rmd" file, and it is successful.

Below is ".rmd" file that tested in ROM Ethernet Boot.

--------

simple.out

-a

-boot

-e

_c_int00 -order L

ROMS

{

ROM1: org = 0x0400, length = 0x0080, memwidth = 32, romwidth = 32

files = { simple.btbl }

}

-----

That has not wrong in my EVB setting.

So I think the RBL offset is not wrong.

Am I right?

Thank you for your reply.

0 ilay nissim over 11 years ago in reply to Sunghwan Kang

Intellectual 530 points

I think Ethernet boot works differently

and determining the offset from flash in spi boot is done deferently

did you try changing the dip switch?

0 Sunghwan Kang over 11 years ago in reply to ilay nissim

Prodigy 170 points

Hello, ilay.

Yes, I checked the 3 different set the dip switch.

My TMDSEVM6657LS has the dip switch in SW3.

But, These are not work, too.

Maybe, I think that my boot table configuarations are wrong something.

How do you think my ".rmd" file and romparse map file?

And my test CCS out file is right for test the ROM SPI Boot?

Thank you so much.

0 Ananth Nagaraj over 11 years ago in reply to Sunghwan Kang

TI__Intellectual 765 points

Hi ,

I remember an issue in rom_parse, one problem is for some reason the read_addr_msw is by default sets to 0x51. Please hard code it to 0x0.Then then try that it might help. I had faced the a similar issue some time back.

Regards,
Ananth

0 Sunghwan Kang over 11 years ago in reply to Ananth Nagaraj

Prodigy 170 points

Hello.

I solved this problem.

I refered below post.

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/229915.aspx?pi267198=1

Thanks.

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ROM SPI Boot problem