proving Hyperlink interface on a new card connecting to C6678

Pradeep,

What card you are trying to connect to C6678? The MCSDK 3.00.00.11 is intended for Keystone II device.

Regards, Eric

For your questions:

1. Though the test informs that it can run in both loopback and board to board mode, what exactly is loopback mode ? Is it a SW loopback ? And when it says as board to board, does it mean two EVM's connected by means of a Hyperlink cross over cable ?

[loopback is the internal loopback at serdes level, it is done in SW by

#define hyplnk_EXAMPLE_LOOPBACK =====> this changed iloop bit

board-to-board means you need have the Hyperlink interface physically connected between two boards. For KS2 EVM and C6678 EVM, it is connected: KS2 EVM ----- KS2 RTM BOC-----Hyperlink cable ----- c6678 EVM]  

2. A littile more infomation about the HW & SW test setup would be helpful.

[HW connection is provided on Q1.

SW:

- make sure the loopback is disabled

- make sure both sides are configured the same baud rate and lane width

- using the GEL file to intialize the DSP first before running the code on a core for both sides

]

 3. As there are two ports of Hyperlink, how to test both the ports ?

[You can select to 0 or 1 for port 0 or port 1

#define hyplnk_EXAMPLE_PORT 0

]

4. Does the same example work for both loopback and board to baord mode ? If yes, then what is the modification to be made? are there any flags that need to be enabled & disabled?

[ Code work for both loopback and board-to-board

- For c6678: only change #define hyplnk_EXAMPLE_LOOPBACK

- For KS 2, SW only supports board-to-board, to test loopback, please check http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/286514.aspx

]

Hi,

i followed the  steps mentioned in the below link.

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/286514.aspx

I did not get the below part in the above link

Then rebuild the test application. Before loading and running, you need to change the EVM use 156.25 MHz reference clock instead of default 312.50 from BMC console:

BMC>hwdbg cmd clkreg show

BMC>clkreg 3.6 0x03

What is BMC console ??

What should be done. I am working with CCS v5

Below is the log of the test. The test hangs.

[C66xx_0] Version #: 0x02000007; string HYPLNK LLD Revision: 02.00.00.07:Sep 2 2013:17:43:29
About to do system setup (PLL, PSC, and DDR)
Power domain is already enabled. You probably re-ran without device reset (which is OK)
Constructed SERDES configs: PLL=0x00000250; RX=0x0046c485; TX=0x000cc305
system setup worked
About to set up HyperLink Peripheral
============================Hyperlink Testing Port 0
========================================== begin registers before initialization ===========
Revision register contents:
Raw = 0x4e902101
Status register contents:
Raw = 0x00003004
Link status register contents:
Raw = 0x00000000
Control register contents:
Raw = 0x00000000
Control register contents:
Raw = 0x00000000
============== end registers before initialization ===========
============== begin registers after initialization ===========
Status register contents:
Raw = 0x04400005
Link status register contents:
Raw = 0xccf00cf0
Control register contents:
Raw = 0x00006202
============== end registers after initialization ===========
Waiting 5 seconds to check link stability
Precursors 0
Postcursors: 19
Link seems stable
About to try to read remote registers

Regards

Pradeep

Hi,

When running the test in board to board test, does the same code be run on both the EVM's ??

What is method of running the software on both the EVM's?

Regards

Pradeep

See http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup

2. Set COM Port to higher value

• When you connect to FTDI mini-USB on the EVM it will provide 2 COM port connections, one to the SOC UART and one to BMC UART.
• The SOC UART will always be the lowest value COM port, for example COM5, and the BMC UART will always be the higher value COM port, for example COM6. (Actual COM PORT values will vary).

3. Set COM port properties appopriately:

• Baud Rate or Bits per second: 115200
• Data Bits: 8
• Parity: None
• Stop Bits: 1
• Flow Control: None

From the BMC console, you need to change Hyperlink clock to 156.25 MHz (the EVM default is 312.50 Mhz), the PDK package only has SERDES setup for 156.25MHz.

Regards, Eric  

You can do loopback as well as board-to-board.

For board-to-board,

HW: connection is Hawking EVM 1---- KS2 RTM BOC -----Molex cable -----KS2 RTM BOC -----Hawking EVM 2

Connect core 0 of EVM1, no boot mode, use gel to initialize DSP

Connect core 0 of EVM2, no boot mode, use gel to initialize DSP

Load the same out file to each core 0 and run via CCS. I have verified the 156.25 MHz ref clock, 6.25 Gb/s and 4x lanes between two Hawking EVMs.

Please make sure the loopback works first then move to board-to-board.

Regards, Eric