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Enabling Cache in application on Codec Engine framework.

Manoj R
Intellectual 390 points

Hi,

I've an application which uses our own decoder.The decoder is integrated to the CE framework and the application is working fine.But the cache is not enabled.How do i enable the cache for DSP memory and ARM memory.

 

In the application in the CCS i enable the cache for DSP used BCACHE functions for which i am linking bios.DM420P library in CCS side.Please let me know where do i link this library in the linux side. Is it while building the server ?? How do i do this ??

Also i would like to know how do i enable the cache for ARM??

 

Please help me as am getting some performance hit if i don't enable cache.

 

Thanks & Regards,

Manoj

  • 0
    TI__Guru*** 125430 points

    Manoj R said:

    The decoder is integrated to the CE framework and the application is working fine.

    So did you implement an XDM 1.0 codec?  If so, you should note that the algorithm itself should not be making any BCACHE calls.  The cache coherence calls on the DSP are actually handled by the Codec Engine framework.  Note, however, that the framework needs you to provide some information in order for it to properly handle the cache operations.  If the CPU reads from an input buffer then you need to "tell" the CE framework.  If the CPU writes to an output buffer then you would also need to tell the framework.  As part of the XDM 1.0 spec there is a variable called accessMask for providing exactly this type of info.  For example:

    XDM 1.0 codec snippet said:

        // Indicate to framework that CPU has read from input buffers
        XDM_SETACCESSMODE_READ(inBufs->descs[0].accessMask);
        XDM_SETACCESSMODE_READ(inBufs->descs[1].accessMask);

        // Indicate to framework that CPU has written to the output buffers
        XDM_SETACCESSMODE_WRITE(outBufs->descs[0].accessMask);
        XDM_SETACCESSMODE_WRITE(outBufs->descs[1].accessMask);

    More information on cache management can be found in the following wiki article:

    http://wiki.davincidsp.com/index.php?title=Cache_Management

    If you're looking at how to actually enable the cache the easiest way is to configure the cache in your BIOS tcf as shown here:

    http://wiki.davincidsp.com/index.php?title=Enabling_64x%2B_Cache

    The Codec Engine framework does not handle cache coherence at all from the ARM side.  Generally if you are using CMEM then the buffers you request are given to use as non-cacheable on the ARM side and so there is no issue with coherence.  If you decide to make the buffers cacheable on the ARM side then you would need to perform appropriate cache operations at the application level.

    Brad

     

     

  • 0 in reply to Brad Griffis
    Intellectual 390 points

    Hi Brad,

     

    Thanks for ur quick response.

    I did the cahce management in the CCS using the BIOS tcf file as shown in the wiki article.In the CCS side my application and Codec work fine withe cache enabled.

    However the problem comes when i build the DSP server in the linux side.I use the tcf file provided by the video copy application in the DVSDK folder with modifications required for our decoder.

    Do i need to modify this  tcf file with appropriate settings for cache enabling in the DSP side??When do i configure the cache (SET  the cache locations ) ....during the build of the server or during the build of the apps.

    If it is in the server side by modifying the tcf can please show an example of how to do it ?? I am only comfortable with GUI settings for tcf in CCS.

     

    Please help.

    Thanks,

    Manoj

     

     

  • 0 in reply to Manoj R
    TI__Guru*** 125430 points

    If you look at the generated tconf file from CCS you can see exactly what needs to be typed.  You would configure the cache for the building of the server.  Since Codec Engine's build relies on the server you should always build the server first and then the app second.

  • 0 in reply to Brad Griffis
    Prodigy 195 points

    Hi,

    Cache enabled by default at the codec engine or it needs to be enabled??Because i was getting more profile counts when i run my code through codec engine(DVTB) than running it on device simulator....

    Can you please get me this information?

  • 0 in reply to gopi krishna12120
    Intellectual 390 points

    I think by defualt cache will be enabled and the sizes of each(L1P ,L1D) will be set to the max size.

    Cross- chcek ur .tci whcih ur server uses .

     

    Thanks,

    Manoj

     

  • 0 in reply to gopi krishna12120
    Intellectual 390 points

    I think cahce will be enabled by default in CE.You can check ur .tci file which is used to build the server to find out how is configured there.

    Thanks,

    Manoj

  • 0 in reply to gopi krishna12120
    TI__Mastermind 37340 points

    Manoj is correct, cache is handled by codec engine.

  • 0 in reply to Juan Gonzales
    TI__Guru*** 125430 points

    The cache configuration is set in the tcf/tci file.  For example:

    codec_engine_2_21/examples/ti/sdo/ce/examples/servers/all_codecs/all_evm3530.tci said:


    var device_regs = {
        l1PMode: "32k",
        l1DMode: "32k",
        l2Mode: "64k"
    };

    The above script sets up the RAM as:

    • L1P:  32KB cache (no SRAM)
    • L1D:  32KB cache (remaining 48KB SRAM)
    • L2:  64KB cache (remaining 32KB SRAM)

    Does that answer your question?  Also, if you're looking for "the final word" you could look at the values of the registers L1PCFG, L1DCFG, and L2CFG as documented in the 64x+ Megamodule Reference Guide.