DM385 UART booting issues

Hi 

You can check board boot mode

Hi, Thanks for the quick response. We checked following items on board and looks ok.

1. All Voltages

2. Boot settings which are exactly same as other bootable boards with pull up an pull down values.

3. No Connectivity issues with connector and SoC ball.

YK

Hello

You can confirm the boot media is correct, 

Because I also experienced the same problem, uart output CCCC

1. no insert SD Card or format

2. no short the pin

in my case, hope to help you.

Hi,

There is no boot media as such..no SD card..what we need is UART boot. There is no CCCCCC chars even in absence of SD card..checked almost everything...all the things seems to be ok but somehow there are no CCCCC chars when power up the board...looks like some issues with the SoC itself..Is it possible that SoC may not be soldered properly or has some errata's or chip itself is not good.

YKFS

Hi YKFS,

Even i have custom board and i am unable to see CCCCC chars. I checked all the boot settings, power supply and clocks. Everything seems to be fine. 

I wanted to know whether your problem was solved? Can you please guide us to over come this situation if your problems were solved?

regards,

Nagendra

Dear Pavel,

I am following the configuration settings according to the data sheet. The BTMODE[4:0] is set to 00001. 

I have checked all the power supply points and clocks. Everything is proper but still i am not able to see any characters on Serial port.

Please help.

regards,

Nagendra

Nagendra SV said:

I have checked all the power supply points and clocks. Everything is proper but still i am not able to see any characters on Serial port.

So you go through steps 1 and 2 of the wiki below

I can suggest you to continue with the other steps.

BR
Pavel

Dear Pavel,

I am unable to probe the register values since the JTAG emulator is not available with us.

I still have a doubt with respect to the clock and configuration circuitry. Please find the clock and configuration circuitry attached with this.

Please check and let me know whether it is correct or not. I can also share you the complete schematics if you can share your email id.

regards,

Nagendraclock_circuit.pdfconfiguration_ckt.pdf

Dear Pavel,

One more doubt. Is the power up sequence very important for DM385 processor? We have not followed power up sequence properly but we are applying Power on reset at the last. Is this the problem for not getting the "CCCCC" on UART port? Please reply.

regards,

Nagendra

Nagendra SV said:

Is the power up sequence very important for DM385 processor?

Yes

Nagendra SV said:

We have not followed power up sequence properly but we are applying Power on reset at the last. Is this the problem for not getting the "CCCCC" on UART port?

Do you mean that you assert (make it 0) the PORn at the last? If yes, this is not correct and might be the root cause of the UART boot issue.

Can you boot your custom board from other boot source? Is UART boot only the problem?

Regards,
Pavel

Nagendra SV said:

I am holding the PORn as 0 for some time and then releasing the PORn to become 1 after certain time. Please let us know whether this is OK or not.

If aligned with DM385 datasheet (7.2.8.1 Power-Up Sequence) then is OK

Hi,

Just now i verified the 3v3, 1v2, 1v35, 1v8 power that is going to DM385 core using the 4 channel oscilloscope. We observed that the power sequencing is fine. May be something else. Please let  us know.

regards,

Nagendra

Nagendra SV said:

We observed that the power sequencing is fine. May be something else. Please let  us know.

If power-up sequence is fine, then the root cause is else

Hi,

We have now connected the JTAG cable (XDS5602 STM from Spectrum Digital) and we have made the following configuration settings:

Now when i try to debug, i am able to run test scripts that come along with the .gel file. I am using IPNC_A8_DDR3.gel file. It is attached with this thread.

I am able to run most of the test scripts like ADPLL test, DDR3 tests, UARTInit tests, etc.

Does it mean that the processor is working? Even after the execution of the scripts, i am unable to see any "CCCCC" coming out from the UART terminal.

Now, even though "CCCCC" does not display, that is fine, but we are unable to write to the flash using nand_flash_writer.out file.

When i try to load the nand_flash_writer.out by using Load program, it gives an error saying: 

CortexA8: File Loader: Verification failed: Values at address 0x80000001 do not match Please verify target memory and memory map.
CortexA8: GEL: File: F:\customers\camera_interface_on_zynq\from_nsketch\2\carbb-ti-rdk.ov2710_dual\utils\nand-writer\bin\nand-flash-writer.out: a data verification error occurred, file load failed.

Please let us know how to over come from this problem and load the nand flash.

regards,

Nagendra

IPNC_A8_DDR3.gel

Nagendra SV said:

Now when i try to debug, i am able to run test scripts that come along with the .gel file. I am using IPNC_A8_DDR3.gel file. It is attached with this thread.

I am able to run most of the test scripts like ADPLL test, DDR3 tests, UARTInit tests, etc.

Does it mean that the processor is working?

We can not state that everything (like DDR3, UART, NAND etc) is working fine, just with running the GEL file successfully. In the DM814x TI EVM, we have HW diagnostic tests (GEL file + c/h files) which are used to check the HW. These tests are available in the below location:

SOFTWARE -> Diagnostic Software -> Base Board -> RevD -> CCS test code -> Base Board

See tests like Boot_Mode, DDR3, NAND, UART0, UART_0_EchoTest. You can try use these tests and/or modify them for your specific custom board (if needed).

Nagendra SV said:

Even after the execution of the scripts, i am unable to see any "CCCCC" coming out from the UART

Detect the boot pins are pullup/down as you expected or not. You can double confirm this by checking the CONTROL_STATUS.SYSBOOT (System Boot Type and the default value comes from BOOT[4:0] pins) to see if it is matched with the HW pullup/down on your board. Use the JTAG emulator to check that register value.

Check the trace vector values to understand the stage of the ROM code. You need to use JTAG to connect the board with CCS.

If you don't see the 'C' output with UART0 in the boot sequence, you may have something wrong with your device. However, you may have an issue with the UART0 data path, or you may have a bad cable. Probe the UART0_TXD/E28 signal/pin and see if you observe any toggling on the signal. If you do, there is most likely a problem with your UART transceiver or cable.

Nagendra SV said:

we are unable to write to the flash using nand_flash_writer.out file.

When i try to load the nand_flash_writer.out by using Load program, it gives an error saying: 

CortexA8: File Loader: Verification failed: Values at address 0x80000001 do not match Please verify target memory and memory map.
CortexA8: GEL: File: F:\customers\camera_interface_on_zynq\from_nsketch\2\carbb-ti-rdk.ov2710_dual\utils\nand-writer\bin\nand-flash-writer.out: a data verification error occurred, file load failed.

Please let us know how to over come from this problem and load the nand flash.

0x80000001 is part of the DDR3 memory map. Can you try to make read/write access from the JTAG with DDR3 addresses 0x80000000, 0x80000004, 0x80000008

See also:

Make sure also you are aligned with the below wiki for flashing the NAND:

BR
Pavel

Hi Pavel,

Thanks for your comments!

I downloaded the supporting files from Mistral link and tried to execute the scripts using JTAG.

All tests are failing. All the tests have been written for TMDXEVM8148 processor. But, our board has DM385 and all the pin outs are different.

Can i get similar downloads somewhere for DM385? so that i can execute the scripts directly.

regards,

Nagendra

Nagendra SV said:

Can i get similar downloads somewhere for DM385? so that i can execute the scripts directly.

I am not aware of such scripts. I would recommend you to check with your DM385 EVM supplier.

Regards,
Pavel

Please contact sales@fossilshale.com for technical support DM385. We have been working on this platform since last 3 years and team is good at it.

Dear Pavel,

An important update:

1. I am able to execute the Configuration register script. It shows the value as 10317. From this, i could make out that the configuration registers are set properly as 10111 as per the data sheet and our expectations.

2. I am able to execute the NAND Flash test script and it shows MFR ID and MFR details correctly. Also it could erase some sectors and it shows "TEST OK" at the end. This means that the NAND Flash interface is also OK

3. I am able to execute the SD Card test script. By inserting the SD card in to slot, it displays test OK. That means the SD interface on the board is OK

4. When i execute the DDR3 configuration script for 533Mhz, and if i try to enter some value at the address 0x80000000 (using memory browser), the value is not getting entered. Instead it shows some junk value. i feel the board needs DDR3 calibration. Please suggest us the steps.

If the DDR3 communication is the problem, will it not display "CCCCCC" in UART? Please reply

Nagendra SV said:

If the DDR3 communication is the problem, will it not display "CCCCCC" in UART? Please reply

Yes

Nagendra SV said:

4. When i execute the DDR3 configuration script for 533Mhz, and if i try to enter some value at the address 0x80000000 (using memory browser), the value is not getting entered. Instead it shows some junk value. i feel the board needs DDR3 calibration. Please suggest us the steps.

Try with the lower frequency possible. See the below wikis:

Regards,
Pavel

Hi,

We are still facing issues and unable to deliver the board to our customer. 

Can we lower the DDR3 CLK frequency coming out of the DDR PLL to 50Mhz? I have a basic oscilloscope. I will try to check the DDR CLK signal if frequency can be brought down to 50Mhz.

I checked the DDR CKE and it always shows 0.68v when the DDR Configuration script is executed. The 0.68v is due to the DDR3_VTT supply from one of the voltage regulator which splits 1.32v to 0.68v and 0.68v.

I tried executing the TI813x DDR3 Init U boot script and i got the message "Values did not converge" and all the parameter values displayed as 0s.

Can we get contact details of any TI Application engineer who can support us?

We tried reaching Avnet and they said to contact Digikey since the chip was purchased from Digikey.

We contacted Digikey and they once again routed us back to TI. TI again said to contact Avnet and finally we did not get any kind of personal support at all.

It would be good if any of the experienced TI engineer to look at the hardware once. Please provide us the right contact person details from Bangalore.

Nagendra SV said:

Can we lower the DDR3 CLK frequency coming out of the DDR PLL to 50Mhz? I have a basic oscilloscope. I will try to check the DDR CLK signal if frequency can be brought down to 50Mhz.

The max frequency DDR3 can support is 533MHz (min period 1.876ns) and min frequency DDR3 can support is 303MHz (max period 3.3ns), see datasheet Table 8-59. Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory Controller

Nagendra SV said:

I checked the DDR CKE and it always shows 0.68v when the DDR Configuration script is executed. The 0.68v is due to the DDR3_VTT supply from one of the voltage regulator which splits 1.32v to 0.68v and 0.68v.

DDR[0]_CKE pin is powered by DVDD_DDR[0] voltage supply, and DVDD_DDR[0] min value is 1.43V for DDR3. See datasheet, section 6.2 Recommended Operating Conditions.

Nagendra SV said:

Can we get contact details of any TI Application engineer who can support us?

We tried reaching Avnet and they said to contact Digikey since the chip was purchased from Digikey.

We contacted Digikey and they once again routed us back to TI. TI again said to contact Avnet and finally we did not get any kind of personal support at all.

It would be good if any of the experienced TI engineer to look at the hardware once. Please provide us the right contact person details from Bangalore.

You should contact your local TI FAE regarding this. See also the below links:

Regards,
Pavel