Hi Champs,
According to XILINX Answer Records #36104, CKE signal is required an external pull-down with a 4.7 kOhm resistor connected to GND to adhere to the DDR2 Spec to drive it to low during RESET as below.
o XILINX AR# 36104
(http://www.xilinx.com/support/answers/36104.html)
- Description
The Memory Controller drives the ODT, CKE, and RESET signals during normal operation
and LOW during initialization, but a pull-down with a 4.7 kOhm resistor connected to
GND is still required to adhere to the DDR2 and DDR3 Memory Standards.
- Solution
Based off the Power-Up Initialization Sequence defined by the DDR2 Spec, CKE and ODT
are supposed to be maintained at a LOW state while applying power. To guarantee this
occurs while the FPGA is being configured (before it can drive CKE and ODT "Low") we
require the pull-down to GND.
So, Dose DM6437 DDR_CKE pin also need to have the 4.7 kOhm external pull-down resistor?
Thanks in advance for your cooperation.
Best regards,
j-breeze
The Memory Controller drives the ODT, CKE, and RESET signals during normal operation and LOW during initialization, but a pull-down with a 4.7 kOhm resistor connected to GND is still required to adhere to the DDR2 and DDR3 Memory Standards.
