AM335x GPMC WAIT Pin Monitoring Control

Daisuke Maeda

Guru 20205 points

WAIT monitored as active freezes the CYCLETIME counter. Does the CYCLETIME counter mean the RDCYCLETIME or the WRCYCLETIME counter?

In the synchronous read, does the asserted WAIT pin extend the current access time before the timing which depends on the programmed WAITMONITORINGTIME value?
Similarly, does the asserted WAIT pin extend the current access time between the timing which depends on the programmed WAITMONITORINGTIME value and the RDACCESSTIME completion?
During the extended current access, all control signals are kept in their current state.

Best regards,

Daisuke

over 11 years ago

0 Biser Gatchev-XID over 11 years ago

TI__Guru**** 393215 points

WAIT monitoring can be configured separately for read and write operations. I do not understand your other two questions. Can you draw a diagram to illustrate?

0 Daisuke Maeda over 11 years ago in reply to Biser Gatchev-XID

Guru 20205 points

Hi Biser,

Thank you for your reply.

When WAITMONITORINGTIME = 0, in the period "A", does the asserted WAIT pin extend the current access time?

When WAITMONITORINGTIME not equal to 0, in the period "B", does the asserted WAIT pin extend the current access time?

When WAITMONITORINGTIME not equal to 0, in the period "C", does the asserted WAIT pin extend the current access time?

Best regards,

Daisuke

0 Biser Gatchev-XID over 11 years ago in reply to Daisuke Maeda

TI__Guru**** 393215 points

I understand now. When the WAIT signal is asserted the CYCLETIME counter is frozen. Upon WAIT deassertion CYCLETIME counter is released and continues counting. When WAITMONITORINGTIME is programmed with a value different from zero it simply adds 1 or 2 GPMC_FCLK cycles before valid data is read/written.

0 Daisuke Maeda over 11 years ago in reply to Biser Gatchev-XID

Guru 20205 points

Hi Biser,

Thank you for your reply.

While the CYCLETIME counter is frozen, are all control signals kept in their current state?

I understand that all access operation stop while the CYCLETIME counter is frozen.

Best Regards

Daisuke

0 Biser Gatchev-XID over 11 years ago in reply to Daisuke Maeda

TI__Guru**** 393215 points

Yes of course, except the GPMC_CLK should be running and some other signals will complete their timing, like nADV for example. This is covered in section 7.1.3.3.8.3 of the AM335X TRM Rev. I.

0 Daisuke Maeda over 11 years ago in reply to Biser Gatchev-XID

Guru 20205 points

Hi Biser,

Thank you for your reply.

Are other control signals, i.e. CSn, BEn, OEn and WEn, kept in their current state?

Our customer wants to know whether the timing of those control signals is extended while the WAIT signal is asserted.

Best Regards

Daisuke

0 Biser Gatchev-XID over 11 years ago in reply to Daisuke Maeda

TI__Guru**** 393215 points

Yes, it should be extended.

0 Daisuke Maeda over 11 years ago in reply to Biser Gatchev-XID

Guru 20205 points

Hi Biser,

Thank you for your reply.

Best Regards

Daisuke

0 Daisuke Maeda over 11 years ago in reply to Biser Gatchev-XID

Guru 20205 points

Hi Biser,

For Wait Monitoring During a Synchronous Read Access, our customer has the problem. The WAIT seems to never work.

In the attached PDF file, there are their configuration and the expected timing diagram.

2018.AM3357_Bus-IF_Timingchart.pdf

It was tried that the RDACCESSTIME was increased and that the level of the WAIT signal was fixed. In the attached archive file, there are the images traced by the logic analyzer.

2744.traces.zip

Why does the WAIT not work?

Best regards,

Daisuke

0 Biser Gatchev-XID over 11 years ago in reply to Daisuke Maeda

TI__Guru**** 393215 points

Hi Daisuke,

I don't see the GPMC_CONFIG[1:7] values that produce this timing anywhere in your post. Can you post them please?

0 Daisuke Maeda over 11 years ago in reply to Biser Gatchev-XID

Guru 20205 points

Hi Biser,

Thank you for your reply.

For the GPMC registers value, please see the attached file.

5165.GPMC_Registor.xls

The GPMC connect to FPGA. The data output from FPGA are checked by an oscilloscope. They are not 0.
The disabled WAIT and the single read access were tried. All the read values are 0.

Best regards,

Daisuke

0 Biser Gatchev-XID over 11 years ago in reply to Daisuke Maeda

TI__Guru**** 393215 points

Hi Daisuke,

A major error I see is that in conf_gpmc_clk register receiver is not enabled. Correct value should be 0x30, not 0x10. This can ruin the whole read operation, as the clock at pin level is also used for input re-timing. Change this setting and let me know how it goes.

0 Daisuke Maeda over 11 years ago in reply to Biser Gatchev-XID

Guru 20205 points

Hi Biser,

Thank you for your reply.

I'm sorry. I should have known and found the error.

Here is the topic about the error: http://e2e.ti.com/support/arm/sitara_arm/f/791/t/319514.aspx

I will let you know how the change goes.

Best regards,

Daisuke

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AM335x GPMC WAIT Pin Monitoring Control