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DDR parameters

1330hayacool7102
Guru 10655 points

hello TI-friends,

after checking http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_DDR3_Init

we got value as below

DDR3 clock frequency 400 MHz
Invert Clkout 0
Trace Length (inches)
Byte 0 Byte 1 Byte 2 Byte 3
CLK trace 3.096 3.096 2.443 2.443
DQS trace 2.025 1.813 1.614 1.514
Seed values (per byte lane)
WR DQS 13 17 F 11
RD DQS 40 40 40 40
RD DQS GATE C3 BB A8 A4
Seed Values to input to program
WR DQS 12
RD DQS 40
RD DQS GATE B2

in arch/arm/include/asm/arch-ti81xx/ddr_defs_ti816x.h.

#define RD_DQS_GATE_LANE3     does this map to C3 or  A4 ??
  • 0
    Guru 10655 points

    hello TI-friends,

    Q1.  #define RD_DQS_GATE_LANE3 does this map to C3 or A4 ??

    one more question is

    Q2. how did we know if the field "Invert Clkout" is zero or other values ??

    we didn't find the any explanation in http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_DDR3_Init

  • 0 in reply to 1330hayacool7102
    Guru 10655 points

    hello TI-friends,

    Q1. 

    Seed values (per byte lane)
    WR DQS 13 17 F 11
    RD DQS 40 40 40 40
    RD DQS GATE C3 BB A8 A4

    how to map RD DQS GATE to following RD_DQS_GATE_LANE3/2/1/0  ??

    #define RD_DQS_GATE_LANE3 0xC3 or  #define RD_DQS_GATE_LANE3 0xA4 ??

    Q2. how did we know if the field "Invert Clkout" is zero or other values ??

     

    Q3.  I found following are different when I download RatioSeed.xml from http://tiprocessors.com/index.php/DM816x_C6A816x_AM389x_DDR3_Init and

    http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_DDR3_Init

     

    following formula seems reasonable. right?

    the following seems to be fixed. Is it correct??

     

  • 0 in reply to 1330hayacool7102
    TI__Prodigy 375 points

    hi

    RD_DQS_GATE is the average of RD_DQS_GATE_LANE3/2/1/0, similarly for WR DQS and RD DQS GATE.

    Basically here is the list of input parameters that you need to provide:

    CK_TRACE_BYTEx (x from 0 .. 3) (units mils i,e. 1/1000 of inch)

    DQS_TRACE_BYTEx (x from 0..3) (units mils i,e. 1/1000 of inch)

    DDR3 frequency (unit MHz)

    INVERT_CLK 0 or 1 depending on which is the case.

    These are used to calculate , WR_DQS[0..3] and RD_DQS_GATE[0..3] , while RD_DQS[0..3] is hard-coded to 0x40. 

    WR_DQS[0] = ((((CK_TRACE_BYTE0-DQS_TRACE_BYTE0)*
                                    180*DDR_FREQUENCY)/1000/1000/1000)*\
                                    256)+(INVERT_CLK*128);

    and similarly for others.

    These values are averaged to get the triplet seed values:

    WR_DQS is AVG(WR_DQS[0..3]

    RD_DQS is AVG(RD_DQS[0..3]

    RD_DQS_GATE  is AVG(RD_DQS_GATE[0..3]).

    These seed values need to be input to the DDR3_SlaveRatio_ByteWiseSearch_TI816x.out program to obtain the MAX,MIN and OPTimum values for each of these 3 parameters.

    Hope this helps.

    thanks & regards,

    Abhilash