Question about AM335x DDR2 Refresh rate configuration

g.f.

Hi,

I have a question about configuration of AM335x DDR2 Refresh rate.

In bl_platform.c(included in AM335x StarterWare), EMIF_SDRAM_REF_CTRL register
is been configured twice with different value as follow:
//////////////////////////////////////////////////////////////
#define DDR2_EMIF_SDRAM_REF_CTRL_VAL1 (0x00004650)
#define DDR2_EMIF_SDRAM_REF_CTRL_SHDW_VAL1 (0x00004650)

#define DDR2_EMIF_SDRAM_REF_CTRL_VAL2 (0x0000081a)
#define DDR2_EMIF_SDRAM_REF_CTRL_SHDW_VAL2 (0x0000081a)

void DDR2Init(void)
{

HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_REF_CTRL) = DDR2_EMIF_SDRAM_REF_CTRL_VAL1;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_REF_CTRL_SHDW) =
DDR2_EMIF_SDRAM_REF_CTRL_SHDW_VAL1;
while(delay--);

HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_REF_CTRL) = DDR2_EMIF_SDRAM_REF_CTRL_VAL2;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_REF_CTRL_SHDW) =
DDR2_EMIF_SDRAM_REF_CTRL_SHDW_VAL2;
}
/////////////////////////////////////////////////////////////////

But in GEL file for AM335x, it's only configured once and the value is 0x81a.
My question is why it's configured twice in bl_platform.c?
Which should customer refer to, the bl_platform.c or Gel configuration?

From following TI wiki page, I guess refer to Gel is fine.
http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips#Setting_Refresh_rate

best regards,
g.f.

over 11 years ago

0 Biser Gatchev-XID over 11 years ago

TI__Guru**** 393215 points

Moving this to Starterware forum.

0 g.f. over 11 years ago in reply to Biser Gatchev-XID

Guru 15520 points

Hi Biser,

Sorry, I should post to Starterware forum.
I will wait for the response from the forum.

best regards,
g.f.

0 Daisuke Maeda over 11 years ago in reply to Biser Gatchev-XID

Guru 20205 points

Hi Biser,

I found a similar question.

http://e2e.ti.com/support/arm/sitara_arm/f/791/t/212989.aspx

We want to know the correct sequence for the refresh rate configuration.

Please give me an answer as soon as possible. Your prompt reply would be appreciated.

Best regards,

Daisuke

0 Baskaran Chidambaram over 11 years ago in reply to Daisuke Maeda

TI__Genius 17370 points

Please treat the configuration in gel file as the right one.

We will update bl_platform.c to be in sync with gel file.

0 Daisuke Maeda over 11 years ago in reply to Baskaran Chidambaram

Guru 20205 points

Hi Baskaran,

Thank you for your reply.

I understand that the following lines in bl_platform.c should be deleted.

//////////////////////////////////////////////////////////////

HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_REF_CTRL) = DDR2_EMIF_SDRAM_REF_CTRL_VAL1;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_REF_CTRL_SHDW) =
DDR2_EMIF_SDRAM_REF_CTRL_SHDW_VAL1;
while(delay--);

//////////////////////////////////////////////////////////////

Is my understanding correct?

Best regards,

Daisuke

0 Daisuke Maeda over 11 years ago in reply to Baskaran Chidambaram

Guru 20205 points

Hi Baskaran,

Our customer is using the configuration procedure same as bl_platform.c for their boards.

Can the following code in bl_platform.c be left as is?

//////////////////////////////////////////////////////////////

HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_REF_CTRL) = DDR2_EMIF_SDRAM_REF_CTRL_VAL1;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_REF_CTRL_SHDW) =
DDR2_EMIF_SDRAM_REF_CTRL_SHDW_VAL1;
while(delay--);

//////////////////////////////////////////////////////////////

Please give me an answer as soon as possible. Your prompt reply would be appreciated.

Best regards,

Daisuke

0 Ramesh Dandamudi over 11 years ago in reply to Daisuke Maeda

TI__Intellectual 1480 points

Hi,

The code mentioned in the snippet can be removed.

Regards,

Ramesh D

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Question about AM335x DDR2 Refresh rate configuration