simple way to disable/enable all program cache L1 and L2 in run time

Genady Kagan

Other Parts Discussed in Thread: TMS320DM642

I am using the TMS320DM642 DSP

There is some simple way to disable/enable all program cache L1 and L2 in run time?

I configure the L2 to be 4 way 128k cache . In some point of may program I want to invalidate the entire program cache and disable it after that.

How can I do it in most simple and way? May be via the 6400 CSL library?

Thanks

over 11 years ago

0 Pubesh over 11 years ago

TI__Mastermind 20790 points

Hi,
When the L1P cache is disabled (000b is written to the L1PMODE field of the L1PCFG register).
When the L1D cache is disabled (000b is written to the L1DMODE field of the L1DCFG register).
When the L2 cache is disabled (000b is written to the L2MODE field of the L2CFG register).
http://www.ti.com/lit/ug/spru871k/spru871k.pdf

In addition that, see the below E2E threads.
http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/115/t/48697.aspx
http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/112/t/11900.aspx

0 Genady Kagan over 11 years ago in reply to Pubesh

Intellectual 320 points

Thanks for fast reponse .

I have more quetions.

1. When I am looking on TI “TMS320C64x/C64x+ DSP

CPU and Instruction Set Refence guid “ on description of PCC field of CSR register , that allows to disable/enable the program cache control, I see the following description:

PCC 0-7h Program cache control mode. This field is ignored on the C64x+ CPU. Writable by the MVC

instruction only in Supervisor mode; not writable in User mode. See the TMS320C64x DSP

Two-Level Internal Memory Reference Guide (SPRU610).

0 Direct-mapped cache enabled

1h Reserved

2h Direct-mapped cache enabled

3h-7h Reserved

Its means , that I can’t disable the program cache ? The 0 value and 2 value I this field , means - Direct-mapped cache enabled ?

2 .I did not found he fields L1PMODE and L1PCFG register in 64XX data sheet, may they exist only in c64+ core ?

0 Pubesh over 11 years ago in reply to Genady Kagan

TI__Mastermind 20790 points

Hi,

For C64x device:

You can use L2MODE field in cache configuration(CCFG) register for disable L2 cache.
For more deails refer the TMS320C64x DSP Two-Level Internal Memory Reference Guide (spru610c)
and TMS320C6000 DSP Cache User’s Guide (spru656)
http://www.ti.com/lit/spru610
http://www.ti.com/lit/spru656

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simple way to disable/enable all program cache L1 and L2 in run time