OMAP-L138 and DDR2 drive strength

Wouter van Herpen

Other Parts Discussed in Thread: OMAP-L138

Hello,

At the moment we are working on a product using a TI OMAP-L138 with a Micron DDR2 memory, type MT47H64M16HR-3.
During our qualification of the product we see that the drive-strength of a read from the DDR2 memory is too strong and exceeds the specified maximum voltage of the OMAP-L138.

In our design we don't use series termination and a write from OMAP to the DDR2 memory device is within its limits. Our design contains 1x DDR2 and is point to point connected. Also the DDR2 chip is close to the OMAP-L138.
Because we want to reduce the drive-strength of the DDR2 chip we use the SDCR.DDRDRIVE bits to set the reduced drive-strength. (Because we don't use a mDDR2 device 1/4 and 1/8 is not available.)

For that we have used the following procedure:

- We use a Micron MT47H64M16HR-3 chip

- The Micron drive strength is determined by the EMRS register, connected to address bus DDR_A[1]

- In SPRUH77A (Dec 2011), chapter 15.2.13, it is mentioned the OMAP’s DDR memory controller is able to issue EMRS commands during initialization sequence

- In SPRUH77A, table 15-13, the EMRS command is described. It is mentioned that DDR_A[1] is based on DDRDRIVE0 from the OMAP’s SDCR register.

- During the initialization (described in SPRUH77A, chapter 15.2.13.1), we set SDCR.DDRDRIVE0 to ‘1’ in step 8, which should correspond to reduced drive strength in the Micron DDR chip

The problem we encounter is that now two out of three boards does not boot/work with the reduced setting. We are still performing measurements to check what exactly is going wrong.

In the meantime we would like to ask the following two questions:

we were not sure whether or not it is possible to use different drive strengths for the OMAP and DDR chip.
So, would it be possible to set the drive strength on the DDR chip to ‘reduced’, and after the DDR controller initialization, change the OMAP’s SDCR register on the fly to set the drive strength to ‘full’ again?
Or is it only possible to have either full or reduced drive strengths on both the OMAP and DDR chip?
To clarify I added the following table:

Nr	OMAP drive strength	Micron DDR chip drive strength	Possible
1	Full	Full	Yes
2	Reduced	Reduced	Yes
3	Full	Reduced	?

We currently think option 1 and 2 are possible, could you tell us if option 3 is also possible?

Is there perhaps something know about this behavior? We checked the TI forum and found a topic on a similar problem. (http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/214910.aspx)
We would like to know if some unreliable behavior could be expected. In the topic the problem occurs when the drive strength is set to 0.5, whereas full, 0.75 and 0.25 drive-strength is working reliable.

over 11 years ago

0 Wouter van Herpen over 11 years ago

Prodigy 40 points

I would like to follow up on these questions after performing additional measurements.

The described DDR reduced drive strenght adjustment gave the following result when measuring:

- DDR to OMAP drive strength was reduced

- OMAP to DDR drive strength had changed little/not at all

- No visible difference in drive strengths between our boards that did and did not boot.

This leads to two additional questions:

1. Maybe we did not correctly interpret the SDCR.DDRDRIVE field. We thought these settings would influence the drive strength in both directions, but it seems only the DDR to OMAP strength was adjusted. Could you verify this?

2. Since there is no visible difference in drive strengths between working/ not working boards, do you have any idea what could cause this behavior? Perhaps a timing related issue?

0 Sivaraj Kuppuraj over 11 years ago in reply to Wouter van Herpen

TI__Mastermind 35645 points

Hi Wouter,

Thanks for your post.

In general, DDR2 supports normal and weak drive strength and mDDR supports full drive strength, 1/4, 1/2, 3/4 drive strength. Only the DDRDRIVE[1:0] bits in SDCR can be configured to control the output impedance of the SDRAM memory which is the drive strength. This bit is writeable only when the BOOTUNLOCK bit is unlocked. So, obviously, the SDCR.DDRDRIVE field configuration would control the drive strengths in both directions,

Please refer DDRDRIVE[1:0] fields of SDCR in table 15-25 in the TRM

There are tolerance limitations for the output drive strength reference which can be calibrated via DDR_ZP pin. Please refer Table 15-1 in the TRM

TRM: http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf

Wiki Resources:

DDR timing spreadsheet: http://processors.wiki.ti.com/index.php/Programming_mDDR/DDR2_EMIF_on_OMAP-L1x/C674x

DDR Interface Drive Strength: http://processors.wiki.ti.com/index.php/DDR_Interface_Drive_Strength

DDR Routing Checklist: http://processors.wiki.ti.com/index.php/DDR_Routing_Checklist#DDR2.2FmDDR.2FDDR3_Routing_Checklist

Regards,

Sivaraj K

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0 Wouter van Herpen over 11 years ago in reply to Sivaraj Kuppuraj

Prodigy 40 points

Hello Sivaraj,

Thanks for your reply and the links.

After reading, one thing still is unclear to me for the function of the DDRDRIVE[1:0] fields. You mentioned in your answer:

'So, obviously, the SDCR.DDRDRIVE field configuration would control the drive strengths in both directions,'

In the second link you posted, it says;

VTP calibration controls the output impedance of the TI SoC DDR pins, while the DDR_DRIVE bits of the DDR controller set the drive strength of the DDR memory

To summarize the different drive strength control options:

VTP Calibration: Controls TI SoC DDR2/mDDR output drive strength
DDRDRIVE0/1 Bits: Control DDR2/mDDR buffer drive strength

This seems conflicting, could you clarify this?

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OMAP-L138 and DDR2 drive strength