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After 667x ethernet boot, is it impossible to use QMSS/NETCP ?

embeddedHolic
Intellectual 405 points

HI, I have read below link.

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/159172.aspx

According to my understanding, QMSS/NETCP(PASS) should be reset if i wanna use again, if once used.

If it is true, there is no way to use qmss/netcp after etherboot.

Do i understand correctly?

I am developing software booting solution over ethernet.

But if the contents in the above link is true, there is no method to download applicaion over ethernet

if the application uses QMSS/NETCP coprocessor.

Give hits about this.

Thanks.

EmbeddedHolic.

  • 0
    Intellectual 405 points

    Hi, experts.

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/200415.aspx

    I have found same issues in above post.

    I have tried as written in the post but failed.

    for( i = 0 ; i < 9 ; i ++)
    {
    pa_padma_txchconf0 = (volatile uint32_t *)( 0x02004400 + 32 * i);
    if( *pa_padma_txchconf0 & (1 << 31) )
    {
    *pa_padma_txchconf0 |= 1 << 30;
    while((*pa_padma_txchconf0 & (1 << 31)));
    }

    }
    #endif
    #if 1
    volatile uint32_t* pa_padma_rxchconf0 = (volatile uint32_t*) 0x02004800;

    // *pa_padma_rxchconf0 |= 0x40000000;
    for( i = 0 ; i < 24 ; i ++)
    {
    pa_padma_rxchconf0 = (volatile uint32_t*)( 0x02004800 + i * 32);
    if(*pa_padma_rxchconf0 & (1 << 31))
    {
    // *pa_padma_rxchconf0 &= ~0x80000000;
    *pa_padma_rxchconf0 |= (1 << 30);
    while((*pa_padma_rxchconf0 & (1 << 31)));
    }
    }

    volatile uint32_t* PDSP0_CTRL = (volatile uint32_t*) 0x2001000;
    volatile uint32_t* PDSP1_CTRL = (volatile uint32_t*) 0x2001100;
    volatile uint32_t* PDSP2_CTRL = (volatile uint32_t*) 0x2001200;
    volatile uint32_t* PDSP3_CTRL = (volatile uint32_t*) 0x2001300;
    volatile uint32_t* PDSP4_CTRL = (volatile uint32_t*) 0x2001400;
    volatile uint32_t* PDSP5_CTRL = (volatile uint32_t*) 0x2001500;

    /* disable PDSP0 */
    *PDSP0_CTRL &= 0xFFFFFFFD;
    /* disable PDSP1 */
    *PDSP1_CTRL &= 0xFFFFFFFD;
    /* disable PDSP2 */
    *PDSP2_CTRL &= 0xFFFFFFFD;
    /* disable PDSP3 */
    *PDSP3_CTRL &= 0xFFFFFFFD;
    /* disable PDSP4 */
    *PDSP4_CTRL &= 0xFFFFFFFD;
    /* disable PDSP5 */
    *PDSP5_CTRL &= 0xFFFFFFFD;

    // Disable Power Domain and Clocks (CSL VERSION)
    if(module_states[3] == 3)
    ModuleStateControl(9, PSC_MODSTATE_DISABLE); // SA Clock Domain
    if(module_states[2] == 3)
    ModuleStateControl(8, PSC_MODSTATE_DISABLE); // CPSW Clock Domain
    if(module_states[1] == 3)
    ModuleStateControl(7, PSC_MODSTATE_DISABLE); // PA Clock Domain
    NetCPPwrDomainControl(PSC_PDSTATE_OFF); // NetCP Power Domain

    States of  CPSW and PA are changed successfully(module SA(mod_num=9) is not enabled in ethernet boot).

    But  the example PA_multicoreExample_exampleProject shows some errors as follows.

    (Packet seems to be corrupted).

    Could anyone give me hints ?

    EmHolic

    [C66xx_0] ************************************************
    *** PA Multi Core Example Started on Core 0 ***
    ************************************************
    Before Power down
    Current state of 3 module 7=3,8=3,9=0
    Power domain is disabled.
    Initializing Free Descriptors.
    QMSS successfully initialized
    CPPI successfully initialized
    PASS successfully initialized
    Ethernet subsystem successfully initialized
    Tx setup successfully done
    Rx setup successfully done
    PASS setup successfully done
    Waiting for all cores to reach the barrier before transmission starts ...
    [C66xx_1] ************************************************
    *** PA Multi Core Example Started on Core 1 ***
    ************************************************
    Waiting for global config...
    QMSS Local successfully initialized
    Rx setup successfully done
    PASS setup successfully done
    Waiting for all cores to reach the barrier before transmission starts ...
    [C66xx_2] ************************************************
    *** PA Multi Core Example Started on Core 2 ***
    ************************************************
    Waiting for global config...
    QMSS Local successfully initialized
    Rx setup successfully done
    PASS setup successfully done
    Waiting for all cores to reach the barrier before transmission starts ...
    [C66xx_3] ************************************************
    *** PA Multi Core Example Started on Core 3 ***
    ************************************************
    Waiting for global config...
    QMSS Local successfully initialized
    Rx setup successfully done
    PASS setup successfully done
    Waiting for all cores to reach the barrier before transmission starts ...
    Packet Transmission Start ...
    Packet Transmission Done.
    Wait for all packets to be Received ...
    Core 3: Packets Sent = 10
    Core 3: Packets Received = 10           <- success
    **********************************************
    *** PA Multi Core Example Ended on Core 3 ***
    **********************************************

    [C66xx_0] Packet Transmission Start ...
    [C66xx_1] Packet Transmission Start ...
    [C66xx_2] Packet Transmission Start ...
    [C66xx_0] Packet Transmission Done.
    [C66xx_1] Packet Transmission Done.
    [C66xx_2] Packet Transmission Done.
    [C66xx_0] Wait for all packets to be Received ...
    [C66xx_1] Wait for all packets to be Received ...
    [C66xx_2] Wait for all packets to be Received ...
    [C66xx_0] Core 0: Packets Sent = 10
    [C66xx_1] VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    [C66xx_2] Core 2: Packets Sent = 10
    [C66xx_0] Core 0: Packets Received = 10
    [C66xx_1] VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    [C66xx_2] Core 2: Packets Received = 10
    [C66xx_0] Wait for all packets to be Received in all cores...
    [C66xx_1] VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    [C66xx_2] **********************************************
    [C66xx_1] VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    [C66xx_2] *** PA Multi Core Example Ended on Core 2 ***
    [C66xx_1] VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    [C66xx_2] **********************************************
    [C66xx_1] VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa
    VerifyPacket: Found an entry in receive queue with swinfo0 = 0x00000000, expected 0xaaaaaaaa

  • 0 in reply to embeddedHolic
    Intellectual 405 points

    If boot mode is set to ethernet boot, and program is loaded by jtag.

    the chip maybe in abnormal state.

    (bootloader doest not exit normal procedure, JTAG reset in the process of boot procedure by force).

    I have tried above code with ethernet boot packet not loaded by jtag, 

    it seems be OK.

    May be helpful to others.

    Holic.

  • 0 in reply to embeddedHolic
    TI__Mastermind 20790 points

    Holic,

    Follow the steps to make sucessful Ethernet boot,

    Steps to build the example:

    1. Run "simple.bat" under "tools\boot_loader\examples\ethernet\simple\". This will build the simple.out and use
       hex6x.exe (delivered in CG tools package) to convert the .out to a boot table file, and then use the
       bconvert64x.exe/bootpacket.exe to convert the hex6x boot table file to the Ethernet boot format data file,
       simple.eth.
      

    Steps to send the simple.eth from the Host to the target DSP

    1. Boot the target DSP in ROM Ethernet boot mode.

    2. Once the DSP boots up, it transmits BOOTP packet at regular interval which will have the MAC ID of the DSP.

    3. Add an ARP entry for the DSP MAC address associating with an IP local to the host. For example if the host PC's IP is 192.168.1.1, then add an ARP entry with the DSP's MAC address associated with IP address 192.168.1.2.

    4. Use the pcsendpkt.exe to send the image to the DSP using the associated IP address. For example
       pcsendpkt.exe simple.eth 192.168.1.2 

    5. Use CCS to connect the EVM, and check that A1 register is set to 0x11223344, that confirms the simple program is received and booted by the ROM boot loader.

     Please refer to the C66x DSP Bootloader User's Guide (http://www.ti.com/litv/pdf/sprugy5) for more details.

  • 0 in reply to Pubesh
    Intellectual 405 points

    Hi,

    I know the ethernet boot (EMACboot) procedure and it's OK.

    The problem i encounter is  PA/CPPI/PacketDMA tear down one.

    But finally i have known is that if i load program via JTAG emulator in ethernet boot mode,

    the tear down is partially OK.

    I have tried with ethernet boot mode, no error(problem) occure.

    Currently i have succedded in multicore ethernet boot.

    I have some other questions.

    1. According to the answer in this community, codes for cores should be generated in global address.

    Is there no way if the codes are generated in local address ?

    2. If i wanna load in DDR , how to in ethernet boot mode ?

    Thanks.