How to adjust HDMI output to fit orignal source in 8148?

You will also need to make sure that the VENC configuration matches the expected range for the HDMI core.

This clamping that you are seeing looks like the VENC is range expanding, possibly with the color space converter.

How are you generating your 'source'? Are you placing known values in the frame buffer or are you using the complete capture-display path?

To analyze exactly what is going on I suggest placing known values directly in the frame buffer initially as a test.

Next, can you create a mapping table where you cycle through input values from 0 to 255 and list what output value you get? This will help me understand if this is a scaling issue or a clipping issue or both.

I am not on the software team so I don't know how software configures the path, but there is a lot of flexibility in each stage and each stage needs to be aligned with the others.

Someone from the software team may be able to directly answer. Hopefully they will chip in :)

BR,

Steve

Dear Steve,

     The method we measure is as below.  We generated a jpg file which gray scale is 0~255. The link structure is

dec-> swMs -> display.  (Use dec to decode jpeg file) Then we measured the HDMI output signal.  Below is the result.  From source 57 ~ 194 is not measured.

 We want to HDMI output signal is just as the same with the orignal source (jpg file).  Especially for color signal.  Please give us some suggections how to achieve it.  Thank you very much.

Sincerely,

James

Hi James,

On HDMI output,  VENC CSC is bypassed since its input and output formats are same ie RGB888. But there is an CSC in the Video pipeline to convert from the YUV444 to RGB888, may be this CSC requires change to output in full range RGB. There are API on M3 to change the CSC coefficients, but i am not sure if it is available on A8. Could you tell me which framework you are using?

Rgds,

Brijesh

Dear Brijesh,

    We use DVR RDK v3.0 GA.  Could you tell me how to change the CSC coefficients?  Thanks a lot.

Sincerely,

James

Hi James,

There is a component called display controller on M3 driver. This component controls all VENCs and these CSCs. One of the create time parameters for display controller is pointer to the CSC configuration. You could pass CSC configuration that you require or you could use one of the predefined CSC configuration. There are different CSC configuration pointers for different CSCs in the path. Please select the one dependin on the display path you are using.

You could get more details about create time parameters in M3 drivers user guide.

Rgds,

Brijesh

Using Encode -> Decode -> SWMS -> Display could change the samples at different places and issue need not be with the display.

1. First as Brijesh mentioned use fbdev to display RGB 888 and check there is no issue.

2. Create pipeline as ipcFramesOut (A8) -> ipcFramesIn (M3VPSS) -> displayLink - This bypasses possible decode quantization and scaler modifications and directly feeds frames to display.

If you see issue with (2) then go in for CSC tuning as suggested by Brijesh.

Dear Badri,

After I survey "High-Definition Video Processing Subsystem (HDVPSS) Technical Reference Manual, I found HD_VENC may affect output result.  But in Fig. "109 HD VENC Block Diagram" in this document, I have questions. If BYPS_CS set 1, the DVO will bypass the signal? Because BYPS_CS is used to select CSC Bypass Mux.  And the bypass output seems no path to DVO.  So DVO must come from CSC result(no bypass)?  If BYPS_CS set 1, then no CSC is done?  I have some confusion about this.  Please give me the correct information so I can do further experiments.  Thanks a lot.

Sincerely,

James

Dear Badri,

      Fig. 109 is as below for quick reference:1057.Fig109.pdf

Thank you very much.

Sincerely,

James

CSC will be bypassed even for the DVO outputs when BYS_SC is set to one. In fact, there is a way to get the input of CSC to the DVO.

Regards,

Brijesh