• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 98 subscribers
  • Views 852 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AIF2 Pi measure issues

zi yang
Intellectual 300 points

Hi , TI engineers, please help me with my problem.

I'm using AIF2 on C6670 to transfer IQ data, we need to mesure the fiber len on running.  I have read the manual but unable to get all point.

My case is LTE FDD 20MHZ, using CPRI.

About PHYT and RADT, I think PHYT is the exactly LTE frame timing , and because the fiber len , tx side should 

send ahead of LTE timing , the RADT is this ahead timing. Am I right?

I know that read the "AT LINK PI CAPTURE" register can get the pi value. but I always get the AIF2 EE "at_ee_link0_pi_err" . Whick  should I do to avoid this error and get the right pi value. Is each time we change the fiber len need I to re config the registers?

Thanks for your reply.

 

  • 0
    TI__Expert 4740 points

    Hi,

    I think you misunderstood something.

    basically, for LTE, PHYT and RADT has the same timing and frame length is also matched as 10 ms. we have additionally DL RADT and UL RADT to adjust timing for each DL and UL scenario but this is not related with your issue.

    delay from long fiber should be OK. only your frame boundary timing will be shifted a certain amount and it doesn't make any trouble. you can see bigger captured pi value in that case on Rx and may see at_ee_pi0_err which means the captured pi is not in pi window. what you only need to do is adjusting pi window values to make your captured pi is in the window. this error is not serious one and only alert that your captured frame has more delay than your original expectation. you can adjust window position by using at_pimax_lk and at_pimin_lk registers.

    Regards,

    Albert

  • 0 in reply to Albert Bae
    Intellectual 300 points

    Hi Albert,

    Thanks for your reply.

    I should start the AIF2 at the accurate LTE timing and set a DL offset, so the tx will be ahead of the real LTE timing to compensate the fiber delay, is this right?

    And even with the at_ee_pi0_err the captured pi is corrent ,  just not within the window. I can still use the pi capture to estimate the fiber len.  Is my view correct?

    Regards,

    ziyang

     

  • 0 in reply to zi yang
    TI__Expert 4740 points

    Right. you can check fiber delay with captured Pi value.

    Regards,

    Albert

  • 0 in reply to Albert Bae
    Intellectual 300 points

     Hi Albert, sorry to trouble you again for my problem in the link below。

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/344750.aspx

    Regards,

    ziyang

  • 0 in reply to Albert Bae
    Intellectual 300 points

    Hi , Albert Bae,

    I want to report an error in the AIF2 CSL library.

    Path:  /PDK/packages/ti/csl/csl_aif2GethwStatusAux.h

    Function: CSL_aif2GetAtLinkPiCapture()

    This function can return the at_pi_capture value, and the register is 32 bit and bit 0~bit 21 are valid, but this inline function only return an Uint8 type that the MSB are clipped. 

    Regards,

    ziyang

     

  • 0 in reply to zi yang
    TI__Expert 4740 points

    Hi,

    Thanks for the catching. I was fixed for Keystone II pdk but it is still there for C6670.

    I'll report this to our SW team and let them update it for the next version.

    Regards,

    Albert