PLL config in syslink example

Dmitriy1

Intellectual 710 points

Other Parts Discussed in Thread: SYSBIOS, OMAPL138

I use syslink messageq example as base for my custom project.

Question: where PLL configuration in the syslink messageq example project located ?

Mentioned project has no GEL file with PLL configuretion.

My project has timer configuration in the SYSBIOS now:

var timer0Params = new Timer.Params();
timer0Params.instance.name = "timer0";
timer0Params.period = 100;
timer0Params.periodType = xdc.module("ti.sysbios.interfaces.ITimer").PeriodType_MICROSECS;
Program.global.timer0 = Timer.create(2, "&ad7606_clkpin_toggle", timer0Params);

can I be sure that I will have interrupt every 100 precise microseconds even if I don't know where is PLL config ?

over 11 years ago

0 Titusrathinaraj Stalin over 11 years ago

TI__Guru** 116100 points

Hi Dimitriy,

Question: where PLL configuration in the syslink messageq example project located ?

I strongly believe that you won't find any PLL configurations in syslink examples since linux kernel has PLL configuration.

If you want to change the PLL0 sysclk1 for DSP then you could try the linux kernel code to modify the DSP clock then run

your syslink examples on target.

can I be sure that I will have interrupt every 100 precise microseconds even if I don't know where is PLL config ?

I hope that you will get exact time delay.

Better to try with second and confirm.

0 Dmitriy1 over 11 years ago in reply to Titusrathinaraj Stalin

Intellectual 710 points

Thank you for respond.

So, PLL config define in the Linux kernel for DSP also. Nice news ))

Ok, I will try to get second delay and will post results.

0 Titusrathinaraj Stalin over 11 years ago in reply to Dmitriy1

TI__Guru** 116100 points

Hi,

Yes, The PLL0 SYSCLK1 DSP is enabled and woke up unless you disabled the DSP in linux.

0 Dmitriy1 over 11 years ago in reply to Titusrathinaraj Stalin

Intellectual 710 points

Interesting, where in the linux present DSP core config? I don't remember mention about DSP in the menuconfig. Or DSP core presented in the linux /dev by the driver?

0 Titusrathinaraj Stalin over 11 years ago in reply to Dmitriy1

TI__Guru** 116100 points

Hi,

By default, The DSP domain has been powered ON and wakeup.

Please refer the page no 183 in OMAPL138 TRM.

We have support in u-boot to disable the DSP wakeup and not powering OFF the DSP completely.

We have to power OFF the DSP if you are not using DSP any more in linux ARM.

http://e2e.ti.com/support/embedded/linux/f/354/p/331656/1158740.aspx

0 Dmitriy1 over 11 years ago in reply to Titusrathinaraj Stalin

Intellectual 710 points

Thanks, Titus!

Titus, what is default value of peripherial internal clock (for timer in my case)?

0 Titusrathinaraj Stalin over 11 years ago in reply to Dmitriy1

TI__Guru** 116100 points

Hi,

Titus, what is default value of peripherial internal clock (for timer in my case)?

Please refer the TRM page no 134 on device clocking chapter.

Timers clock domain will be ASYNC3

http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/337872.aspx

0 Dmitriy1 over 11 years ago in reply to Titusrathinaraj Stalin

Intellectual 710 points

Titus,

I use 24Mhz external quartz. So, default clock source for the timer P2 is ASYNC3, by default ASUNC3 use PLL0_SYSCLK2 for the clock.
I use Linux from TI's bsp. As I understood, If I use syslink, PLL configured from Linux. So, default value of PLL0_SYSCLK2 228 Mhz. Right?

What is default ASYNC3?

In which file of Linux TI's BSP it is defined?

0 Titusrathinaraj Stalin over 11 years ago in reply to Dmitriy1

TI__Guru** 116100 points

Hi,

I use Linux from TI's bsp. As I understood, If I use syslink, PLL configured from Linux. So, default value of PLL0_SYSCLK2 228 Mhz. Right?

I hope so, since you are configured the processor speed to 456MH.

Also, ASYNC3 domain get clock from either PLL0_SYSCLK2 or PLL1_SYSCLK2 and it depends on AYNC3_CLKSRC bit of CFGCHIP3 register.

What is default ASYNC3?

PLL1_SYSCLK2 because it helps keeping the peripherals on this domain insulated from CPU frequency changes caused by DVFS.

In which file of Linux TI's BSP it is defined?

arch/arm/mach-davinci/da850.c

Refer "da850_set_async3_src" function to decide the ASYNC3 clock source.

0 Dmitriy1 over 11 years ago in reply to Titusrathinaraj Stalin

Intellectual 710 points

Thank you! It was VERY VERY helpfull!

0 Titusrathinaraj Stalin over 11 years ago in reply to Dmitriy1

TI__Guru** 116100 points

Hi Dimitriy,

I'm glad that you got clarified.

Thanks for your update.

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PLL config in syslink example