DM8148 PCIe Gen2 again

Stephan

Other Parts Discussed in Thread: AM3871

Hi,

we are successfully running the Mistral DM8148 EVM as PCIe endpoint. However, we can only get it working at gen1 2.5GT speed. As soon as we remove a line in the startup code forcing LINK_CAP to single speed, we run into the often described issue that the PCIe registers become inaccessible and Linux reports an external abort on non-linefetch error.

So my questions are:

1) is it possible at all to run the DM8148/AM3871 at gen2 speed? What are the restrictions? Would a Windows RC be able to communicate at gen2 speed? Would the endpoint be able to busmaster at 5GT from/to the RC?

2) What exactly means the entry in the TI Wiki about "gen2 only in one direction"

3) What are the steps to enable gen2 speed?

Thanks,

Stephan

over 11 years ago

0 Pavel Botev over 11 years ago

TI__Guru**** 170625 points

Stephan,

Yes, the DM814x PCIe supports Gen2 in RC and EP mode.

http://processors.wiki.ti.com/index.php/DM81xx_AM38xx_PCI_Express_Root_Complex_Driver_User_Guide

Listed below are the various features supported by DM81xx as a PCI Express Root Complex.

DM814x: Gen1 and Gen2 operation with x1 link supporting 5 GT/s raw transfer rate in single direction

http://processors.wiki.ti.com/index.php/DM814x_AM387x_Power_Estimation

PCIe

1. Status: If PCIe is used, choose "Active", else choose "Off"

2. Mode: Select the mode of operations for PCIe (Gen 1 , Gen 2(Full Duplex: 1X, Full Duplex: 2X))

DM814x datasheet:

The device PCIe supports the following features:
- Supports Gen1/Gen2 in x1 or x2 mode

DM814x TRM:

19.2.11.1 DMA Support in RC Mode
In addition, the master port on PCIe port can issue read/write accesses that have been initiated by remote
PCI Express device. The interconnect fabric should provide sufficient capacity to serve 85% of 2 Gbps (4
Gbps if operating in Gen2) per PCIe link in each direction.

19.2.11.2 DMA Support in EP Mode
The approximate data rate for each of these transactions will be about 85% of 2 Gbps (4Gbps in Gen2
mode) in each direction on each PCIe lane.

Please have a look into the below links for some Gen2 restrictions:

http://processors.wiki.ti.com/index.php/TI81XX_PCIe_FAQs#I_have_connected_TI81xx_to_a_GEN2_capable_device_and_link_is_established_fine_but_why_does_the_Link_Speed_field_in_Link_Status_register_still_show_GEN1_.282.5_GT.2Fs.29.3F

DM814x Silicon errata, Advisory 3.0.10 - PCIe Gen2 Mode: PCIESS Corruption of Round Trip Latency Time and Replay Time Limit Bits (PL_ACKTIMER Register)

Regards,
Pavel

0 Stephan over 11 years ago in reply to Pavel Botev

Prodigy 110 points

Sorry but all this doesn't really help. After enabling LTSSM_EN_VAL with LINK_CAP = 0xXXXXXX11 (x1, gen1) the endpoint LTSSM state goes to 0x11, as expected. Then I'm setting LINK_CAP to 0xXXXXXX13 (x1, gen2) and trigger link retraining by setting DIR_SPD to one.

The next thing I see is that the link state goes to RCVRY_LOCK, then sometimes to RCVRY_SPEED. Then the power management interrupt fires. But I cannot reset the interrupt because at that time the PCIE application registers are already inaccessible (powered down in the HW I guess). At this point I always end up with the Linux kernel invalid access error.

Can you advice what is the correct register write sequence to switch to gen2 mode?

And what does it mean if the PM interrupt fires? Has the device been disabled by the RC because of communication errors?

Has anyone had success using DM8148 in EP mode and gen2 speed?

Thanks,

Stephan

0 Pavel Botev over 11 years ago in reply to Stephan

TI__Guru**** 170625 points

Stephan,

I found one thread for DM816x RC working at x2 gen2:

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/145159.aspx

I found also the below code which indicates DM814x PCIe should be able to work with x1 gen2:

ti-ezsdk_dm814x-evm_5_05_02_00/board-support/linux-2.6.37-psp04.04.00.01/arch/arm/mach-omap2/pcie-ti81xx.c

static int ti81xx_pcie_setup(int nr, struct pci_sys_data *sys)
{

..........

/*
   * TI81xx devices do not support h/w autonomous link up-training to GEN2
   * form GEN1 in either EP/RC modes. The software needs to initiate speed
   * change.
   */
   __raw_writel(DIR_SPD | __raw_readl(
               reg_virt + SPACE0_LOCAL_CFG_OFFSET + PL_GEN2),
           reg_virt + SPACE0_LOCAL_CFG_OFFSET + PL_GEN2);

   /*
   * Check if we need to force the link to x1 lane. This is particularly
   * applicable for TI81XX devices which are single lane while the PCIe
   * module's registers show x2 as lane configuration (e.g., LINK_CAP
   * register shows x2 on TI814X devices while they actually support
   * single lane only). Setting force_x1 flag directs us to force x1 in
   * link configurations avoiding sending misleading information from
   * PCIe configuration dump (e.g., 'lspci -vv' output).
   */
   if (force_x1) {
       u32 val;

       val = __raw_readl(reg_virt + SPACE0_LOCAL_CFG_OFFSET +
               LINK_CAP);
       val = (val & ~(0x3f << 4)) | (1 << 4);
       __raw_writel(val, reg_virt + SPACE0_LOCAL_CFG_OFFSET +
               LINK_CAP);

       val = __raw_readl(reg_virt + SPACE0_LOCAL_CFG_OFFSET + PL_GEN2);
       val = (val & ~(0xff << 8)) | (1 << 8);
       __raw_writel(val, reg_virt + SPACE0_LOCAL_CFG_OFFSET + PL_GEN2);

       val = __raw_readl(reg_virt + SPACE0_LOCAL_CFG_OFFSET +
               PL_LINK_CTRL);
       val = (val & ~(0x3F << 16)) | (1 << 16);
       __raw_writel(val, reg_virt + SPACE0_LOCAL_CFG_OFFSET +
               PL_LINK_CTRL);
   }

I will further check with the PCIe driver experts whether the DM814x PSP supports PCIe EP in x1 gen2 mode.

Best regards,
Pavel

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