SRIO Extended address

Mark Samson

I've a question about the Address Extension feature of the SRIO pheripheral.

I want to send data directly to an external DDR3 module using SRIO
Until now I have used 0x80000000 as a destination address for writing into the first 2 GB of the DDR3

The question is: it's possible to use in reception and in transmission an extended address of 36 bit?
And in that case how doest it works? The DSP uses that address as a physical address instead as a logical address?

over 11 years ago

0 Ganapathi Dhandapani95 over 11 years ago

TI__Mastermind 28085 points

Hi Mark,

It is possible but you want to use more than 2GB means you can use the XMC to translate the logical address space (32bit) to physical address space (36bit).

DSP uses 32bit logical address. Please take a look at below link:

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/309132.aspx

Thanks,

0 Mark Samson over 11 years ago in reply to Ganapathi Dhandapani95

Intellectual 355 points

my question was different.

I was asking if using the extended srio address it's possible to access directly to all DDR3 memory space passing to the DSP the phyisical address instead of the logical address

0 Ganapathi Dhandapani95 over 11 years ago in reply to Mark Samson

TI__Mastermind 28085 points

No, It is not possible.

0 Daisuke Maeda over 9 years ago in reply to Ganapathi Dhandapani95

Guru 20205 points

Hi Ganapathi,

The logical 32-bit address is used by the SRIO master port for the internal access but it should be not translated by the XMC's MPAX feature since the XMC is inside a CorePac. Does it invariably match the logical 32-bit address space described in Table 2-2 on the datasheet(SPRS691E) regardless of the MPAX configuration?

Best regards,

Daisuke

0 Ganapathi Dhandapani95 over 9 years ago in reply to Daisuke Maeda

TI__Mastermind 28085 points

The memory map table shows only the default MPAX configuration of DDR3 memory space. For the extended DDR3 memory space access (up to 8GB), see the MPAX configuration details in C66x CorePac User Guide.

0 Daisuke Maeda over 9 years ago in reply to Ganapathi Dhandapani95

Guru 20205 points

Hi Ganapathi,

Thank you for your reply.

I want to know about the address space used by the SRIO master port, not the CorePacs. It should be not translated by the XMC's MPAX feature since the XMC is inside CorePacs.

Best regards,

Daisuke

0 Daisuke Maeda over 9 years ago in reply to Ganapathi Dhandapani95

Guru 20205 points

Hi Ganapathi,

Does the address space used by the SRIO master port be translated by the XMC's MPAX feature?

Best regards,

Daisuke

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SRIO Extended address