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Hello,
I am developing a custom dm8148 board.
I am using the GMII PHY.
Although I have to ping the target board between the host,
Destination Host Unreachable
But it will be displayed on the console.
The test environment
HOST <-> 1000BaseHUB (Logitec LAN-GSW05 / PH) <-> TARGET
In the console output of the target board,
PHY: 0:00 - Link is Up - 1000 / Full
It is output.
But I fail to ping.
What is wrong?
u-boot evm.c
int board_init(void)
{
u32 regVal;
/* Do the required pin-muxing before modules are setup */
set_muxconf_regs();
nor_pad_config_mux();
/* setup RMII_REFCLK to be sourced from audio_pll */
__raw_writel(0x4, RMII_REFCLK_SRC);
if (PG2_1 <= get_cpu_rev()) {
/*program GMII_SEL register for RGMII mode */
// __raw_writel(0x30a,GMII_SEL);
/*program GMII_SEL register for GMII mode */
__raw_writel(0x0,GMII_SEL); // brastvision setting
}
/* Get Timer and UART out of reset */
/* UART softreset */
regVal = __raw_readl(UART_SYSCFG);
regVal |= 0x2;
__raw_writel(regVal, UART_SYSCFG);
while( (__raw_readl(UART_SYSSTS) & 0x1) != 0x1);
/* Disable smart idle */
regVal = __raw_readl(UART_SYSCFG);
regVal |= (1<<3);
__raw_writel(regVal, UART_SYSCFG);
/* mach type passed to kernel */
gd->bd->bi_arch_number = MACH_TYPE_TI8148EVM;
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
gpmc_init();
#ifndef CONFIG_NOR
/* GPMC will come up with default buswidth configuration,
* we will override it based on BW pin CONFIG_STATUS register.
* This is currently required only for NAND/NOR to
* support 8/16 bit NAND/NOR part. Also we always use chipselect 0
* for NAND/NOR boot.
*
* NOTE: This code is DM8168 EVM specific, hence we are using CS 0.
* Also, even for other boot modes user is expected to
* on/off the BW pin on the EVM.
*/
gpmc_set_cs_buswidth(0, get_sysboot_bw());
#endif
return 0;
}
static void pcie_pll_config()
{
/* Powerdown both reclkp/n single ended receiver */
__raw_writel(0x00000002, SERDES_REFCLK_CTRL);
__raw_writel(0x00000000, PCIE_PLLCFG0);
/* PCIe(2.5GHz) mode, 100MHz refclk, MDIVINT = 25,
* disable (50,100,125M) clks
*/
__raw_writel(0x00640000, PCIE_PLLCFG1);
/* SSC Mantissa and exponent = 0 */
__raw_writel(0x00000000, PCIE_PLLCFG2);
/* TBD */
__raw_writel(0x004008E0, PCIE_PLLCFG3);
/* TBD */
__raw_writel(0x0000609C, PCIE_PLLCFG4);
/* pcie_serdes_cfg_misc */
/* TODO: verify the address over here
* (CTRL_BASE + 0x6FC = 0x481406FC ???)
*/
//__raw_writel(0x00000E7B, 0x48141318);
delay(3);
/* Enable PLL LDO */
__raw_writel(0x00000004, PCIE_PLLCFG0);
delay(3);
/* Enable DIG LDO, PLL LD0 */
__raw_writel(0x00000014, PCIE_PLLCFG0);
delay(3);
/* Enable DIG LDO, ENBGSC_REF, PLL LDO */
__raw_writel(0x00000016, PCIE_PLLCFG0);
delay(3);
__raw_writel(0x30000016, PCIE_PLLCFG0);
delay(3);
__raw_writel(0x70000016, PCIE_PLLCFG0);
delay(3);
/* Enable DIG LDO, SELSC, ENBGSC_REF, PLL LDO */
__raw_writel(0x70000017, PCIE_PLLCFG0);
delay(3);
/* wait for ADPLL lock */
while(__raw_readl(PCIE_PLLSTATUS) != 0x1);
}
void prcm_init(u32 in_ddr)
{
/* Enable the control module */
__raw_writel(0x2, CM_ALWON_CONTROL_CLKCTRL);
#ifdef CONFIG_SETUP_PLL
/* Setup the various plls */
audio_pll_config();
sata_pll_config();
#if 1 // TODO 140731 need gigE
pcie_pll_config();
#endif
modena_pll_config();
l3_pll_config();
ddr_pll_config();
dsp_pll_config();
iva_pll_config();
iss_pll_config();
usb_pll_config();
/* With clk freqs setup to desired values,
* enable the required peripherals
*/
per_clocks_enable();
#endif
}
