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How to avoid hole reusing again

Hengwei Xiang
Intellectual 360 points
Other Parts Discussed in Thread: SYSBIOS

Hi,

   The following map fill is genrated:

00897940 00000010 ti.csl.ae66 : csl_tsc.oe66 ($Tramp$S$$CSL_tscRead)
00897950 00000010 --HOLE-- [fill = 0]

.switch.2 
* 0 00897950 00000010 
00897950 00000010 HDL_PDU.obj (.switch:HDL_PushToLmacQue)

Why is the section filled with hole and the address reused by .switch.2?then how to avoid this?

When DSPs boot image from flash, .switch.2 is loaded first ,then the hole filled with 0s at the same address of .switch.2.That is ,the hole cover the .switch.2.How to resolve this case?

Thanks.

Hengwei

  • 0
    TI__Guru* 81335 points

    Hi Hengwei,

    1. What is the DSP Part number ? (I assume C6670) EVM or custom board?

    2. What is the package used and its version?

    3. Could you please elaborate the issue reported?

    4. Are you running example project or custom project? How to re-produce etc?

    Thank you.

  • 0 in reply to Raja
    Intellectual 360 points

    Hi Rajasekaran  ,

          1.Yes,I use C6770 custom board.C6670 boots image from EEROM by I2C first,then the application in EEROM executes and loads the real projects image which store in NOR-Flash to each core.

          2.The package  version is pdk_C6670_1_0_0_21.

          3.I  posted a thread in E2e before,please see this link:http://e2e.ti.com/support/development_tools/compiler/f/343/p/354680/1256282.aspx#1256282.

         4.We  re-produce the custom project based on SYS/ BIOS for each core.The SYS/BIOS version is bios_6_33_05_46.

    Thanks and regards.

    Hengwei

  • 0 in reply to Hengwei Xiang
    TI__Guru* 81335 points

    Hi Hengwei,

    We are working experts to answer your query. Thank you for your patience.

  • 0 in reply to Raja
    Intellectual 360 points 
    Hi ，
    is there any new result?
  • 0 in reply to Hengwei Xiang
    TI__Guru** 116020 points

    Hi Hengwei,

    I don`t see this issue with the sample boot images I have on my machine. Can you provide details of which utility generates the hole? Is it the linker or the hex6x command utilitiy.? Are you using Multicore application deployement utility ? IF yes, is it used in bypass prelink or prelinker mode?

    The creation of hole and placement of sections is typically handled by the TI compiler tools (linker, hex6x) and can be controlled using the options you pass to the linker. Is the HOLE created after building the SYSBIOS project and is filed later or do you see the placement of switch.2 in the same map file.

    Can you please generate a duplicate post on the TI compiler forums as I believe the compiler experts will be able to help you handle this issue.

    Regards,

    Rahul