DDR3 parameters for ZQ_CONFIG Register ARM AM3352; trouble when heating DDR

trichet christophe

Expert 2025 points

Hello,

for DDR3 ZQ_CONFIG Register, in u-boot, the function config_ddr(short ddr_type) in emif4.c loads this register
with the line : emif_regs = &ddr3_emif_reg_data; and with definition in ddr_defs.h : #define DDR3_ZQ_CFG 0x50074BE4; this register programmation is done in MLO/u-boot.

When we are heating the DDR3 of board, even a little bit, our board hangs up.

1) Does linux re-program this register ?

2) the values of programmation are for Micron MT41J128M16JT-125 (as put in comment in ddr_defs.h) should we adapt so values to our DDR (MT41K256M16HA-125) ?

I have changed DDR3_ZQ_CFG to 0x50070BE4 with no improvment when heating the product.

N.B

i have made calibration and found the values :

//[CortxA8] ***************************************************************
[//CortxA8] PARAMETER                       MAX | MIN | OPTIMUM | RANGE
//[CortxA8] ***************************************************************
//[CortxA8] DATA_PHY_RD_DQS_SLAVE_RATIO    0x06d | 0x002 | 0x037 | 0x06b
//[CortxA8] DATA_PHY_FIFO_WE_SLAVE_RATIO   0x13d | 0x000 | 0x09e | 0x13d
//[CortxA8] DATA_PHY_WR_DQS_SLAVE_RATIO    0x079 | 0x011 | 0x045 | 0x068
//[CortxA8] DATA_PHY_WR_DATA_SLAVE_RATIO   0x0b6 | 0x047 | 0x07e | 0x06f
//[CortxA8] ***************************************************************
so i changed in ddr_defs.h
//#define DDR3_RD_DQS       0x3B
//#define DDR3_WR_DQS       0x85
//#define DDR3_PHY_WR_DATA   0xC1
//#define DDR3_PHY_FIFO_WE   0x100

to the new values :
#define DDR3_RD_DQS       0x37
#define DDR3_WR_DQS       0x45
#define DDR3_PHY_WR_DATA   0x7E
#define DDR3_PHY_FIFO_WE   0x9E

Thanks for any suggestion

best regards

over 11 years ago

0 Biser Gatchev-XID over 11 years ago

TI__Guru**** 393215 points

Please follow the guidelines given here:

http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips

http://processors.wiki.ti.com/index.php/AM335x_DDR_PHY_register_configuration_for_DDR3

There is also an excellent step-by-step tutorial here:

http://processors.wiki.ti.com/index.php/Sitara_Linux_Training:_Tuning_the_DDR3_Timings_on_BeagleBoneBlack

trichet christophe said:
When we are heating the DDR3 of board, even a little bit, our board hangs up.

To what temperature do you heat the board?

0 trichet christophe over 11 years ago in reply to Biser Gatchev-XID

Expert 2025 points

Hello

thanks for the reply

I have calibrated the DDR3 using the links you provided.

What register should be considered for RAM derivation when heating is done ?

thanks

Best regards

0 Biser Gatchev-XID over 11 years ago in reply to trichet christophe

TI__Guru**** 393215 points

DDR3 memory should perform with no change in settings up to 85 degrees Celsius case temperature. Above that it must operate at 2X refresh rate (only if it's industrial or automotive grade memory).

0 trichet christophe over 11 years ago in reply to Biser Gatchev-XID

Expert 2025 points

Hello

is it possible under linux to read zq_config register (see if the value put in it during u-boot is still OK) ?

How can i read it : have you a code source example for reading this register ?

thanks

best regards

0 Miroslav Kiradzhiyski XID over 11 years ago in reply to trichet christophe

TI__Mastermind 25235 points

Hi Trichet,

You can write a simple C program to read from /dev/mem. Example snippet:

void read_mem(unsigned int reg_addr, unsigned int *reg_val, int access_width)
{
    int fd;
    void *mem_map, *mem_addr;
    fd = open("/dev/mem" , O_RDWR|O_SYNC);
    mem_map = mmap(0, MEM_SIZE, PROT_READ|PROT_WRITE, MAP_SHARED, fd, reg_addr & ~MEM_MASK);
    mem_addr = mem_map + (reg_addr & MEM_MASK);
    printf("0x%08X\n", *(uint32_t*)mem_addr);
    close(fd);
}

Best regards,
Miroslav

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DDR3 parameters for ZQ_CONFIG Register ARM AM3352; trouble when heating DDR