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AM3358 DDR3 Software Levelling

Valid Welds
Prodigy 100 points
Other Parts Discussed in Thread: AM3358

Hi,

I am working on a prototype board that is based on the AM335x but with AM3358 StarterKit SDRAM (don't ask why..). I am currently using WindRiver Workbench (as the target OS is VxWorks). Needless to say the DDR3 doesn't work and the only way I can see to obtain the correct register values is to run the software levelling algorithm on CCS.

So, if we buy CCS and a XDS200 probe (the proto has a 20-pin jtag facility), and all goes well, should this be sufficient to determine these regiseter values?

Of course I'd need a modified AM3358 StarterKit GEL file and the DDR3_slave_ratio_search_auto.out file.

Also, am I correct in saying the DDR3_slave_ratio_search_auto.out file is run by CCS and not on-board?


Thanks in advance,

David.

e AM3358 StarterKit

  • 0
    TI__Guru**** 393215 points

    Hi David,

    David Wells said:
    am I correct in saying the DDR3_slave_ratio_search_auto.out file is run by CCS and not on-board?

    It's loaded through CCS but runs on-board. If you follow these guidelines you will be able to determine your register setting successfully:

    Since you mention that you have Starter Kit-like DDR3 memory layout and the memory is not working please check the following:
    The Starter Kit has a Vtt regulator for the Vtt termination resistors voltage. This is enabled by a GPIO signal coming from the AM335X (DDR_VTT_EN, AM335X pin C18 on the Starter Kit). This signal needs to be driven high for the Vtt regulator to operate, otherwise the DDR3 will not function.
  • 0 in reply to Biser Gatchev-XID
    Prodigy 100 points

    Thanks Biser.

    The process appears to be:
    1 determine EMIF timing registers based on the memory configuration (aided by AM335x_DDR_register_calc_tool.xls)
    2 estimate starting points for the DDR PHY registers using RatioSeed_AM335x_boards.xls
    3 determine optimum DDR PHY register values using code composer studio, AM3358_StarterKit.gel and DDR3_slave_ratio_search_auto.out

    It’s step 3 I’m interested in at the moment. I can set up register values and download and run code using my existing on-chip debug tool. So with regards DDR3_slave_ratio_search_auto.out:
    1) where in memory is this code run (surely not DDR3 because that’s not set up yet)?
    2) is the source code for this available please?

    I’m not adverse to buying a TI probe and CCS but I’d need to be convinced it would help to follow this process on our prototype board.

    Thanks,
    David.

  • 0 in reply to Valid Welds
    TI__Guru**** 393215 points

    David Wells said:
    1) where in memory is this code run (surely not DDR3 because that’s not set up yet)?

    DDR is setup by the .GEL file that's run before loading the .OUT file.

    David Wells said:
    2) is the source code for this available please?

    No, this is not available.

  • 0 in reply to Biser Gatchev-XID
    Prodigy 100 points

    Biser Gatchev-XID said:

    1) where in memory is this code run (surely not DDR3 because that’s not set up yet)?

    DDR is setup by the .GEL file that's run before loading the .OUT file.

    So is the DDR 'kind-of' working and the phy parameters are just 'tweaked'? I don't understand - I thought DDR3 would either work (with confidence) or not work. Can you explain please?

    David Wells said:
    2) is the source code for this available please?

    No, this is not available.

    Where is the .out file loaded / executed from please?

    [/quote]

  • 0 in reply to Valid Welds
    TI__Guru**** 393215 points

    David Wells said:
    So is the DDR 'kind-of' working and the phy parameters are just 'tweaked'? I don't understand - I thought DDR3 would either work (with confidence) or not work. Can you explain please?

    Yes, that' roughly what's done. DDR accesses are performed within an iteration routine to find the optimal values. I can't help about the .out file question.

  • 0 in reply to Biser Gatchev-XID
    Prodigy 100 points

    Thanks for your help Biser. I've got it working now. I had used the AM335x_EVM_DDR2_LE.reg file as a starting point but had not set up the PLLs correctly and had incorrect and missing values in my .reg file. I bought a TMDSEMU100V2U-20T - JTAG EMULATOR, 20PIN, XDS200 PROBE and used that with CodeWarrior to perform the software levelling process. Attached file shows my additions so that it might help somebody.

    2677.AM3358_DDR3_mods.reg.txt
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    REM *******************************************
    REM CF CONFIGURATION
    REM *******************************************
    REM Halt processor firstly before implement the CF options
    HA
    CF TAR AM3358 ; OPERATION
    CF VECTOR IGNORE ; OPERATION
    CF SB SB ; OPERATION
    CF RST YES ; OPERATION
    CF TRESET ACTIVE ; OPERATION
    CF HRESET ENABLE ; OPERATION
    CF CMDRST BOTH ; OPERATION
    CF INVCI YES ; OPERATION
    CF SPOWER YES ; OPERATION
    CF RTP NO ; OPERATION
    CF TRPEXP BREAKPOINTONLY ; OPERATION
    CF LENDIAN YES ; OPERATION
    CF CLK 16 ; OPERATION
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Regards,

    David.

  • 0 in reply to Valid Welds
    TI__Guru**** 393215 points

    Thanks David, for sharing your solution on the forum.