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DDR3 wordwise SW leveling

ranchu
Guru 20755 points

Hello,

I would like to ask about page http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_DDR3_Init_Wordwise_SWleveling :

It described how to enter values inside the excel for generating seed, but in the example it seems that all 4 bytes should be inserted.
1. In case it is 16-bits, should I fill only byte 1 and byte 2 ?

2. When doing that I got wr_dqs = 1 and I suspect something is wrong. Please see the attached excel.

4572.RatioSeed_TI814x EMIF0.xlsx8345.RatioSeed_TI814x EMIF1.xlsx

Thanks,

Ran

  • 0
    TI__Guru**** 170625 points

    Ran,

    Ran S. said:
    I would like to ask about page http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_DDR3_Init_Wordwise_SWleveling :

    I think you should follow the below wiki:

    http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot_Wordwise_SWleveling

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Guru 20755 points

    Hi Pavel,

    Thanks very much for the quick response.

    I follow the wiki, but it has some staff not well understood, it seems that the page example is for 32-bits interface, but what about 16-bits interface ? Should I fell only byte1-2 in the excel and it shall return correct seed ? I suspect something is wrong becuase the first seed in both EMIF0 and EMIF1 is 1.

    Thanks,

    Ran

  • 0 in reply to ranchu
    TI__Guru**** 170625 points

    Ran,

    Ran S. said:
    I follow the wiki, but it has some staff not well understood, it seems that the page example is for 32-bits interface, but what about 16-bits interface ?

    I think this wiki is for both 32-bit and 16-bit DDR interface. On the other wiki, we have:

    http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot#ReadMe_First

    ReadMe First

    The purpose of this document is to describe the approach to fine tune the DDR PHY on TI814x devices with SW leveling.SW leveling can be done in two methods

    • Byte wise SW leveling (For 32 bit DDR interface only)

    Data macro for each byte lane is leveled independently. The Slave ratio search program will calculate optimal values for each byte lane.

    • Word wise SW leveling (For 32 bit or 16 bit DDR interface)

    The Slave ratio search program will calculate common optimal value that works for all four byte lanes.

    Recommendation: It is advised to perform byte wise leveling to compensate for the trace length delays for each byte lanes accurately, especially at higher frequencies of operation as compared to the word wise leveling.

    This wiki page talks about Byte wise SW leveling.For word wise SW leveling follow the link http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot_Wordwise_SWleveling