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C6457 Datasheet

Toshio Ushikubo
Mastermind 9620 points
Other Parts Discussed in Thread: TMS320C6457

Would kindly tell me the questions about the content of  the datasheet in TMS320C6457 (SPRS582A)?

1.  In page of  37 of SPRS582A, it describes the content of the terminal EMU0 and EMU1 terminal and it adds (3).

      I think it include some additional information.

      But, there is no information in them.

      Would you kindly tell me their additional information?

2. In page of  142 of SPRS582A, it describes the physical address of  PLLDIV3 with 0x029A 0120.

    In page of 146 of SPRS582A, it describes the physical address of PLLDIV3 with 0x029A 015C.

    Which addrees is correct for PLLDIV3?

3. In page of 146 of SPRS582A, it describes RATIO after reset value is 2h, it means that devides the frequency by 3.

    In that case, SYSREFCLK equals to 1.2GHz, it becomes to 1.2GHz/3=400MHz .

   However, in page of 141, Table 7-24 describes Max is 333MHz, 400MHz exceeds 333MHz.

  Is it possible ?

  • 0
    Intellectual 535 points

    Hello Toshio,

    1. Really TI forgot to tell what mean "(3)" near EMU0/EMU1!

    I can propose that this pin targeted for XDS  debug system connection for multiprocessor chain and HSRTDX...

    2. Wait kindly TI's  explanations.... 8-)

    3. You a right with calculation,  but just after reset core doesn't clocked at 1.2 GHz, because multiply  PLLM (described at page 144) equal 0 and typically SYSREFCLK=60MHz, so SYSCLK3 near to 20MHz. Then if you change PPLM you should pay attention for SYSCLK* dividers for their correct generation, imho.

     

  • 0
    Intellectual 535 points

    I found  some unclear statements in C6457 documents. May be anybody clarify me about:

    1. SPRAAV7B—October 2009 TMS320TCI6484 and TMS320C6457 DSPs Hardware Design Guide Page 39 of 50  said:

    "If the EMIF64 peripheral is not used, *most* EMIF64 inputs can be left unconnected"

     

    What are *rest* pins that should not be left unconnected????

     

     Thanks

     

     

  • 0
    Intellectual 290 points

    Hi Toshio ,

     

    For PLLDIV3, I saw this typo as well. I suspect that the correct address is 0x029A 0120 as this is the address found in the GEL file for my C6457 EVM board from Lyrtech. I have not yet verified this though.

    // PLL 1 definitions (DSP clk and subsystems)
    #define PLL1_BASE           0x029A0000
    #define PLL1_DIV3           (PLL1_BASE + 0x120)   // DIV3 divider

    May I ask please -- if you have a working design using the C6457, could you tell me which emulator you are using to connect to the JTAG port? I have a Spectrum Digital XDS560R and am encountering an error code on the connect operation (described on this thread: http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/112/t/40631.aspx).

     

    Thanks,

    - Craig