Two channels for UPP on c6657

Elnur Babishov

Hello!
I try to use UPP on c6657 with both channels (A and B). Channel A corresponds DMA I. Channel B coresponds DMA Q.
How many ISRs must be for this case: one for both channels or two for each channel?

over 10 years ago

0 Pubesh over 10 years ago

TI__Mastermind 20790 points

Elnur Babishov,

The uPP peripheral generates eight interrupt events, all tied to internal DMA Channels I and Q.
The uPP peripheral automatically combines all interrupt events into a single chip-level interrupt.
Individual events may be enabled using the uPP interrupt enable set register (UPIES) and disabled using the uPP interrupt enable clear register (UPIEC).
The ISR must be able to handle multiple events before returning.

Find the pseudo code in the section "Sample Interrupt Service Routine" at the keystone UPP user guide.
This wiki page will give you, basic details and how to configure the UPP,
http://processors.wiki.ti.com/index.php/Introduction_to_uPP
The following E2E post gives you more details about how interrupt handled in the UPP module,
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/284300
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/202118/987854

0 Elnur Babishov over 10 years ago in reply to Pubesh

Intellectual 895 points

Thank you, Pubesh.

Yes, I read already.

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Two channels for UPP on c6657