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AM437x GPMC signal behavior

g.f.
Guru 15520 points

Hi,

I have questions about AM437x GPMC.

I will use GPMC and data width is 16bit.

What will be happen with data alignment, if byte and word(16bit) accessing to the odd byte boundary?

I guess the data aligning won't be performed if accessing to the odd byte boundary, so I guess the behavior of GPMC signal will be as following:

Case1: Single Write Access

(1)Writing one byte "0xAA" to the address 0x1

(2)Writing two bytes "0xAABB" to the address 0x1

In Case1-(1), will the lower address, BE(Byte Enable) and data be as following?

-Lower address GPMC_A[16:1] = 0x00_00

-Byte Enable(BE0/BE1) = (01)b

-GPMC data(16bit) = 0x**_AA (** means don't care)

In Case1-(2), will the access be divided into twice as following?

First access:

-Lower address GPMC_A[16:1] = 0x00_00

-Byte Enable(BE0/BE1) = (01)b

-GPMC data(16bit) = 0x**_AA (** means don't care)

Second access:

-Lower address GPMC_A[16:1] = 0x00_01

-Byte Enable(BE0/BE1) = (10)b

-GPMC data(16bit) = 0xBB_** (** means don't care)

 

Case2: Single Read Access

The data(0x00112233) is stored in the address 0x0 of external memory.

(1)Reading one byte from the address 0x1

(2)Reading two bytes from the address 0x1

In Case2-(1), will the lower address, BE(Byte Enable) and GPMC data be as following?

-Lower address GPMC_A[16:1] = 0x00_00

-Byte Enable(BE0/BE1) = (01)b

-GPMC data(16bit) = 0x**_11 (** means don't care)

In Case1-(2), will the access be divided into twice as following?

First access:

-Lower address GPMC_A[16:1] = 0x00_00

-Byte Enable(BE0/BE1) = (01)b

-GPMC data(16bit) = 0x**_11 (** means don't care)

Second access:

-Lower address GPMC_A[16:1] = 0x00_01

-Byte Enable(BE0/BE1) = (10)b

-GPMC data(16bit) = 0x22_** (** means don't care)

best regards,

g.f.

  • 0 in reply to Biser Gatchev-XID
    Guru 15520 points
    Hi Biser,

    Thank you for the reply.

    I checked the post which you attached.
    It seem that my understanding was uncorrect.

    I fixed the GPMC data part as following,
    but I'm not sure yet. Can you please check the following?

    Case1-(1)
    BE0 is High, BE1 is low
    GPMC data(16bit) will be 0xAA_**(** is not valid)

    Case1-(2)
    First access:
    BE0 is High, BE1 is low
    GPMC data will be 0xAA_**(** is not valid)

    Second access:
    BE0 is Low, BE1 is High
    GPMC data will be 0x**_BB(** is not valid)

    Case2-(1)
    BE0 is High, BE1 is low
    GPMC data(16bit) will be 0x11_**(** is not valid)

    Case2-(2)
    First access:
    BE0 is High, BE1 is low
    GPMC data(16bit) will be 0x11_**(** is not valid)

    Second access:
    BE0 is Low, BE1 is High
    GPMC data will be 0x**_22(** is not valid)

    best regard,
    g.f.
  • 0 in reply to g.f.
    TI__Guru**** 393215 points

    Please read the whole thread. The BE0/1 signals do not work exactly as expected. As far as I can remember they work only on write accesses.

  • 0 in reply to Biser Gatchev-XID
    Guru 15520 points
    Hi Biser,

    Thank you for the reply.

    I read the whole thread and checked the AM437x TRM(spruhl7b) page.1136 "9.1.3.3.8.3.12 Byte Enable".
    And I understand as follow:

    * If access is asynchronous/synchronous multiple read access, BE0/BE1 is asserted low.
    * If access is asynchronous/synchronous single write/read access, BE0/BE1 is asserted or nonasserted.

    If one byte read access to the odd address, it will work
    but if two bytes read access to the odd address, it will be multiple byte read access because it's outof boundary
    so that it won't work.

    So, single/multiple write or single read access to odd address will work.
    Is my understanding correct?

    best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Guru**** 393215 points

    As I understand it, BE0/1 will toggle only on 8-bit single R/W. On multiple reads BE0/1 will always both be asserted. I'm sorry, I don't have the hardware to check this.

  • 0 in reply to Biser Gatchev-XID
    Guru 15520 points
    Hi Biser,

    Thank you for the reply.
    So, I should only use byte single Read/Write access against odd address.

    best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Guru* 85960 points
    g.f.,
    what are you trying to interface to? An FPGA? Do you have any requirements that you are trying to meet? Or just exploring GPMC capabilities?

    regards,
    James
  • 0 in reply to JJD
    Guru 15520 points
    Hi James,

    Thank you for the reply.

    Actually this question is from my customer.
    They are trying to interface to FPGA.
    And they just exploring GPMC capabilites.

    best regards,
    g.f.