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SRIO trains intermittently

Michael Stich
Expert 1505 points

I have a C6678 EVM trying to talk to an FPGA via SRIO in 1 port 4x mode.  It eventually needs to run at 5 GBps, but at the moment I'm running 1.25  When I try an initialize the SRIO, I sometimes will get PORT_Ok on the first try, sometimes after many dozens of tries (it retries every 2 seconds), sometime longer than I care to wait. When it does link up, it says the port width is 1x, the data seems to make it to the fpga properly, and the link never seems to fail.  I've verified that VMIN is 15 per other posts, and that the pll is locked before doing other configuration per 

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/258414

RX equalization is full adaptive, and there are no pre/post cursor weights set.

I'm not sure what to look at now. 

Looking at the LaneN_stat registers, there is a bit that says says TX long/short reach that is set by "srio_laneN_tx_mode"  I cannot find this bit anywhere.  I've got 3 connectors and probably 35 cm of length, so I think it is probably long reach, but I can't seem to change it. 

Also, there is are bits for RX_TYPE indicating short run, but I can't seem to set those either. 

Can someone suggest how to debug this?  Need to get all 4 lanes going. Thanks very much in advance.

Mike

  • 0
    TI__Mastermind 28085 points
    Hi,

    I am not clear on your setup. Please provide more detail about your SRIO configuration.

    For my understanding, SRIO is working properly on 4x mode at 5 Gbps and not working on 1x mode at 1.25 Gbps. Is it correct?

    Thanks,
  • 0 in reply to Ganapathi Dhandapani95
    Expert 1505 points

    I have an EVM with an adapter board on the AMC connector which then has an SRIO connector on that.  A cable runs from the adapter board conenctor to the fpga board which also has a connector. The cable and its connectors are designed for SRIO speeds I believe. 

    The SRIO does NOT work at 4x at all, even at 1.25 Gbps.  It is set up to run 4x mode but always drops back automatically to 1x for some reason.  I haven't even tried 5 Gbps yet.

    Mike

  • 0 in reply to Michael Stich
    TI__Mastermind 28085 points
    Hi,

    Thanks for your detailed information.

    Have you using TI provide SRIO example for your testing? If yes share the project name.

    Please take a look at MCSDK SRIO Throughput test code. It support SRIO loopback and normal mode. First you can run the loopback mode test on your DSP it working fine then you can run normal mode test.

    MCSDK Path: C:\ti\pdk_C6678_1_1_2_6\packages\ti\drv\exampleProjects\SRIO_TputBenchmarkingTestProject

    Refer section "5.1 Single EVM internally looped back" and "9.1 Setting up C-I-C connection mode (core to core, internal loopback)" on SRIO_Benchmarking_Example_Code_Guide document.

    Doc Path: \ti\pdk_C6678_1_1_2_6\packages\ti\drv\srio\test\tput_benchmarking\docs\SRIO_Benchmarking_Example_Code_Guide.

    Thanks,
  • 0 in reply to Ganapathi Dhandapani95
    Expert 1505 points

    I have based my code off the device_srio_loopback.c code which I can no longer find the post that I got it from.  It is from TI and is a simple loopback at the logical layer.  The first thing I did was modify it to loop back at the SERDES layer. It works fine, links back to itself in 4x mode reliably. 

    The problems happen when I try and link to the fpga.  It has a lot of difficulty obtaining "Port_Ok" status. and when it does, it has dropped back to 1x instead of 4x. What exactly has to happen for Port_Ok?  And how does one debug why it isn't happening?

    Attached is my srio initialization for reference. 

    Thanks for any help.      Mike

    srio.zip

  • 0 in reply to Michael Stich
    TI__Mastermind 28085 points
    Hi,

    SRIO works properly on loop-back mode means the SRIO initialization is fine. Have you using the same SRIO configuration on FPGA side? Have you validated the hardware connection between SRIO and FPGA?

    Please refer the below thread, it should be help you to debug the SRIO connection
    e2e.ti.com/.../971310

    Thanks,
  • 0 in reply to Ganapathi Dhandapani95
    Expert 1505 points

    Thanks for the pointer.  I'm still digging thru the information. Most of it I've already done, but there are a few new posts.  

    It seems likely the issue is in the connections, since when it does connect after dropping back to a single lane, the data does get transferred correctly as far as we can tell using debug tools on the fpga. So possibly the links are borderline in terms high speed data integrity. 

    In all the posts I've looked at, there seems to be no discussion on how to set things for non-optimal links.  On the rx side, it seems like all you can do is set the equalizer for full adaptation, true?    On the tx side, I've seen no discussion on how to set pre/post cursor tap weights.  Is it generally not necessary to use these?  How does one go about adjusting them if necessary?

    Mike