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Hello Community! We have made a design with 3 DACs (DAC7811) in "daisy chain mode" connected on a McBSP-Port of a C6713B.
The DACs need a coherent 48Bit data frame followed by a rising edge on frame sync for load and update the DAC.
Currently we are using the McBSP mode where the frame sync are generated out of the sample rate generator SRGR (SPRU580G,page 23).
So with single phase frame and fixed FWID of 48Bits everything works fine. The disadvantage is, we have a fixed sample rate wich
depends on FPER and CLKGDV inside SRGR.
In the future we want to use the update function as callable function with no specific time interval (no fixed sample rate).
So we think about SPI Mode where the frame sync signal is generated by DXR-to-XSR-copy. I wrote a function, where 3 16Bit values
are written to the McBSP data transmit register consecutively. The problem is, the McBSP generate 3 accesses with a data width of 16Bit.
Or respectively i will get no coherent 48Bit access within one frame sync periode.
So i think it will be a good idea to change XFRLEN1 to 3 words in a phase. Perhaps this will be solve the problem with
the non coherent frame sync. I visit the signals on the scope. Eureka! I see the coherent frame periode...
But the problem is: With this configuration i will get 54 clock periods instead of the expected 48 clock periods.
So it seems to be that this doesn't work...
So i ask my self now is this possible at all?
How can I realize such a functionality?
