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where to change clock settengs in u-boot and kernel for DM8168

Massimiliano Cialdi
Expert 1995 points

We use DM8161 with kernel cloned from arago linux-omap3 and u-boot from arago u-boot-omap3

We need to change the clock setting, to match the specification stated in Rev F datasheet.

I can find some #define to change in u-boot arch/arm/include/asm/arch-ti81xx/clocks_ti816x.h (FAPLL mult, div, freq and post div) but no sysclk PRMC divider is defined.

In the kernel I can find #define (in arch/arm/mach-omap2/cm-regbits-81xx.h) of FAPLL mult, div, freq and post div again but no sysclk PRMC divider.

I wonder if kernel overwrite settings done in u-boot. And where are set (or should be set) the sysclk divider, u-boot or kernel?

best regards

max

  • 0
    TI__Guru**** 170625 points

    Max,

    We have a u-boot patch for DVR RDK:
    http://arago-project.org/git/projects/?p=u-boot-dvr-rdk-dm81xx.git;a=commit;h=84808db76d9f5f830d07a653a9a2b55261af38d4

    You can port this patch to the EZSDK u-boot omap3 code base.

    See also the below e2e thread and PDF attached in this thread.
    e2e.ti.com/.../415727

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Expert 1995 points

    Pavel Botev said:

    We have a u-boot patch for DVR RDK:
    arago-project.org/.../projects;a=commit;h=84808db76d9f5f830d07a653a9a2b55261af38d4

    You can port this patch to the EZSDK u-boot omap3 code base.

    What about SYSCLK divider settings? Where these registers should be initialized?

    And what about clock settings in the kernel? In file arch/arm/mach-omap2/fapll_ti816x.c there are functions (eg. ti816x_fapll_program()) that write N, P, FREQ and M. These functions are not called in startup, but I am not sure that these functions may be called in other circumstances, overwriting the u-boot settings.

    The patch you suggest doesn't take into account kernel. For example in file arch/arm/mach-omap2/cm-regbits-81xx.h of linux-dvr-rdk-dm81xx are defined the values for MAIN PLL:

    #define TI816X_MAINPLL_N                                64
#define TI816X_MAINPLL_P                                0x1
#define TI816X_MAINPLL_INTFREQ1                         0x8
#define TI816X_MAINPLL_FRACFREQ1                        0x800000
#define TI816X_MAINPLL_MDIV1                            0x2
#define TI816X_MAINPLL_INTFREQ2                         0xE
#define TI816X_MAINPLL_FRACFREQ2                        0x0
#define TI816X_MAINPLL_MDIV2                            0x1

    that would makes ARM run about at 987MHz and DSP 813MHz, but the VCO output would be 1728MHz that is aout of specs (VCO output frequency should be less than 1600MHz). If ti816x_fapll_program() is called the settings written by u-boot were overwitten (with wrong, potentially dangerous values).

    And once again, where and when the kernel set the sysclk values?

    more in details:

    where and when u-boot (should) set the sysclk values?

    where and when kernel (should) set the sysclk values?

    who should set sysclk values between kernel and u-boot (or both)?

    best regards

    max

  • 0 in reply to Massimiliano Cialdi
    TI__Guru**** 170625 points

    DM816x does not support DVFS so new FAPLL changes are limited to uboot, not within Linux, PLLs are not reconfigured at run-time

  • 0 in reply to Pavel Botev
    TI__Guru**** 170625 points
    Regarding SYSCLKs you can made a search in u-boot and kernel, and reconfigure the values according to the SYSCLKs calculator tool:

    e2e.ti.com/.../1485220

    Regards,
    Pavel
  • 0 in reply to Pavel Botev
    Expert 1995 points

    Pavel Botev said:
    Regarding SYSCLKs you can made a search in u-boot and kernel, and reconfigure the values according to the SYSCLKs calculator tool:

    e2e.ti.com/.../1485220

    According to your opinion, where is better to reconfigure SYSCLK, either kernel or u-boot? In my opinion is better u-boot to centralize clock generation setup.

    best regards

    max

  • 0 in reply to Pavel Botev
    Expert 1995 points

    I have another question about u-boot:

    the function ddr_pll_init_ti816x() in file board/ti/ti8168/evm.c (or board/ti/ti8168/dvr.c) is this:

    static void ddr_pll_init_ti816x(u32 sil_index, u32 clk_index)
{
	u32 ddr_pll_ctrl=0;

	/* Sequence to be followed:
	 * 1. Put the PLL in bypass mode by setting BIT2 in its ctrl reg
	 * 2. Write the values of N,P in the CTRL reg
	 * 3. Program the freq values, divider values for the required output in the Control module reg
	 * 4. Note: Loading the freq value requires a particular bit to be set in the freq reg.
	 * 4. Program the CM divider value in the CM module reg
	 * 5. Enable the PLL by setting the appropriate bit in the CTRL reg of the PLL
	 */

	 /* If the registers have been set by the ROM code dont do anything
	  */

	ddr_pll_ctrl = __raw_readl(DDRPLL_CTRL);
	ddr_pll_ctrl &= 0xFFFFFFFB;
	__raw_writel(ddr_pll_ctrl, DDRPLL_CTRL);

	ddr_pll_ctrl = __raw_readl(DDRPLL_CTRL);
	ddr_pll_ctrl &= 0xFFFFFFF7;
	ddr_pll_ctrl |= 8;
	__raw_writel(ddr_pll_ctrl, DDRPLL_CTRL);

	ddr_pll_ctrl = __raw_readl(DDRPLL_CTRL);
	ddr_pll_ctrl &= 0xFF;
	ddr_pll_ctrl |= (DDR_N<<16 | DDR_P<<8);
	__raw_writel(ddr_pll_ctrl, DDRPLL_CTRL);

	/* 10usec delay */
	ddr_delay(10);

	__raw_writel(0x0,DDRPLL_PWD);

	__raw_writel(((0<<8) | DDR_MDIV1), DDRPLL_DIV1);
	ddr_delay(1);
	__raw_writel(((1<<8) | DDR_MDIV1), DDRPLL_DIV1);

	__raw_writel((1<<31 | 1<<28 | (DDR_INTFREQ2<<24) | DDR_FRACFREQ2), DDRPLL_FREQ2);
	__raw_writel(((1<<8) | DDR_MDIV2), DDRPLL_DIV2);

	__raw_writel(((0<<8) | DDR_MDIV3), DDRPLL_DIV3);
	ddr_delay(1);
	__raw_writel(((1<<8) | DDR_MDIV3), DDRPLL_DIV3);
	ddr_delay(1);
	__raw_writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3), DDRPLL_FREQ3);
	ddr_delay(1);
	__raw_writel((1<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3), DDRPLL_FREQ3);

	ddr_delay(5);

	/* Wait for PLL to lock */
	while((__raw_readl(DDRPLL_CTRL) & 0x80) != 0x80);

	ddr_pll_ctrl = __raw_readl(DDRPLL_CTRL);
	ddr_pll_ctrl &= 0xFFFFFFFB;
	ddr_pll_ctrl |= 4;
	__raw_writel(ddr_pll_ctrl, DDRPLL_CTRL);

	__raw_writel(0x1, DDR_RCD);

}

    first of all the procedure implemented here and the procedure explained in Ref Man (par. 1.10.3.1.2.1.1), are slightly different.

    My question is about delay (the call to ddr_delay() function). These delay are not described neither in Ref Man nor in Errata. I wonder if these delays are really necessary, and where they are described. For example the delay values are taken from some document, are calculated (how?) or are some guessed values?

    In function main_pll_init_ti816x() there is no delay. I have to write a function to set up audio pll (I could name it audio_pll_init_ti816x()) and I don't know if the delay are needed and which values.

    Another question is about the comment:

    /* If the registers have been set by the ROM code dont do anything
 */

    How can I know if registers have been set by the ROM code?

    best regards

    max

  • 0 in reply to Massimiliano Cialdi
    TI__Guru**** 170625 points

    mastupristi said:
    According to your opinion, where is better to reconfigure SYSCLK, either kernel or u-boot? In my opinion is better u-boot to centralize clock generation setup.

    Yes, you can do this in u-boot, in the board file. Just make sure that linux kernel and firmware will not overwrite the u-boot settings. If you have question regarding specific SYSCLK let me know.

    Regards,
    Pavel

  • 0 in reply to Massimiliano Cialdi
    TI__Guru**** 170625 points

    mastupristi said:
    My question is about delay (the call to ddr_delay() function). These delay are not described neither in Ref Man nor in Errata. I wonder if these delays are really necessary, and where they are described. For example the delay values are taken from some document, are calculated (how?) or are some guessed values?

    These seems to me like fixing some DDR3 stability issues (which might be specific for the TI EVM). Can you try to remove these delays. Does your DDR PLL lock up and behave properly?

    You can also have a look in the evm816x.gel where we do not have delay for the DDRPLL init/config.

    mastupristi said:
    In function main_pll_init_ti816x() there is no delay. I have to write a function to set up audio pll (I could name it audio_pll_init_ti816x()) and I don't know if the delay are needed and which values.

    I do not think you need delays for audio PLL.

    mastupristi said:

    Another question is about the comment:

    /* If the registers have been set by the ROM code dont do anything
 */

    How can I know if registers have been set by the ROM code?

    If registers are not in their default/reset values (documented in the TRM) then the ROM code (1st stage bootloader) was made some modifications in these registers. See DM816x TRM, chapter 25 ROM Code. In this chapter you will find more info regarding ROM Code and which registers are modified by the ROM Code.

    Regards,
    Pavel