SRIO issue between DSP and FPGA

Hi Mani,
Please provide the following information:

1. Share your FPGA RapidIO Specification REV?

2. DSPs SRIO configuration detail? (ports and baud rate)

3. Have you running same code on all DSP's?

Thank you.

There are many e2e discussed about DSP SRIO and FPGA on other side. Please refer them, it may help to solve the issue.
e2e.ti.com/.../213726
e2e.ti.com/.../299638
e2e.ti.com/.../354938
e2e.ti.com/.../357422
Thank you.

Hi,

Please find details below

1. FPGA RapidIO Specification REV : Xilinx Kintex 7 FPGA, SRIO Gen2 V3.0

2. DSPs SRIO configuration detail? (ports and baud rate)
One Port, 4 Lane, 3.125Gbps, Ref Clk 156.25MHz

3. Have you running same code on all DSP's?
Yes. There are two C6674 DSPs, both DSPs runs with same SRIO code, where DSP0 has extra code to configure External SRIO Switch, there is no difference apart from that.

Hi,

In your setup, two DSP and one FPGA are connected via SRIO switch. Is it correct?

Have your observed the DSP SRIO ready signal is getting low (going down) only for FPGA sent data to DSP?
Is the DSP to DSP transfer is works fine?

Thanks,

Hi,

Yes, both DSPs and one FPGA are connected over SRIO switch.

Observing DSP SRIO ready signal between DSPs is not possible.

Yes, As per my experiments I was able to transfer data between one DSP to other without any data loss, and using single 'Srio_sockSend_DIO' of data size 6Kilo Bytes, TTYPE: Srio_Ttype_Swrite_DEFAULT, FTYPE: Srio_Ftype_SWRITE (data sizes above 6K yet to be tested).

Tried sending data again from FPGA to both DSPs and it is observed that DSP SRIO ready signal getting low, when almost data transferred for 2400Bytes.

My Application details:

- It is combination of both Ethernet, and SRIO application

- SRIO current window size is 128 queues each of 64bytes
- Ethernet - 128 queues each of 512bytes

Attached my Config (.cfg).benchmarking.cfg (Hope this may give some hints, if i'm doing something wrong)

Thanks

Mani Kumar

Hi,

I tested the SRIO Throughput example between two DSP (C6678) successfully with up-to 8K Bytes payload size.

Thanks,

Hi,

Looks like its a very good value.

May I know what is the behavior if data size is more than 8KB, any data loss observed or API itself returning any error?

Any clues regarding my issue why DSP SRIO ready signal getting low when FPGA transmitted data size if >= 2400 bytes?

Thanks
Mani Kumar

Hi,

Any clues regarding my issue why DSP SRIO ready signal getting low when FPGA transmitted data size if >= 2400 bytes?

Is the FPGA and DSP placed on the same board?
Have you using the common power for both DSP and FPGA?

Thanks,

Hi,

Yes, FPGA and DSP placed on the same board.

Yes, Common power is used between DSP and FPGA.

Thanks

I think it is not a software configuration issue on your setup. Please try to check the electrical problems between the two devices.

Have you using common reference clock for DSP and FPGA?

Thanks,

Hi,

After verifying my board Hardware schematics, DSP and FPGA have individual reference clocks.

Please let me know if there are any other parameters to be verified.

Thanks