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6657 srio port can't be ok

user4379902
Prodigy 90 points

I use the program modified from D:\ti\pdk_C6657_1_1_2_6\packages\ti\drv\exampleProjects\SRIO_LoopbackDioIsrexampleproject.The rate is 3.125G,4x.

/* Configure SRIO to operate in Normal mode. */
CSL_SRIO_SetNormalMode (hSrio,0);
CSL_SRIO_SetNormalMode (hSrio,1);
CSL_SRIO_SetNormalMode (hSrio,2);
CSL_SRIO_SetNormalMode (hSrio,3);

/* Assuming the link rate is 2500; program the PLL accordingly. */
CSL_BootCfgSetSRIOSERDESConfigPLL (0x251);//0x233

/* Configure the SRIO SERDES Receive Configuration. */
CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x00440495);
CSL_BootCfgSetSRIOSERDESRxConfig (1, 0x00440495);
CSL_BootCfgSetSRIOSERDESRxConfig (2, 0x00440495);
CSL_BootCfgSetSRIOSERDESRxConfig (3, 0x00440495);

 /* Configure the SRIO SERDES Transmit Configuration. */
 CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00180795);
 CSL_BootCfgSetSRIOSERDESTxConfig (1, 0x00080795);
 CSL_BootCfgSetSRIOSERDESTxConfig (2, 0x00080795);
 CSL_BootCfgSetSRIOSERDESTxConfig (3, 0x00080795);

/* Configure the path mode for the ports. */
// for(i = 0; i < 4; i++)
CSL_SRIO_SetPLMPortPathControlMode (hSrio, 0, 4);

while (CSL_SRIO_IsPortOk (hSrio, 0) != TRUE); //4x  just need to see port 0

It runs to while (CSL_SRIO_IsPortOk (hSrio, 0) != TRUE); //4x  just need to see port 0, and it can't run out this. Is that no matter fpga program is right or not, it will complete initiation if I confige registers right?

  • 0
    TI__Mastermind 28085 points

    Hi,

    Your code changes is fine for SRIO loopback to normal mode operation. Try to check the PFGA SRIO port status.

    There is also another SRIO example in the MCSDK that can run in loopback or board to board. I have tested this example on loopback or board to board modes successfully. Better to try this SRIO example for your testing

    MCSDK Path: C:\ti\pdk_C6657_x_x_x_x\packages\ti\drv\exampleProjects\SRIO_TputBenchmarkingTestProject

    Refer section "5.3 Two EVMs connected using breakout cards" and "9.4 Setting up B-E-B connection mode (board to board, external interface)" on 3073.SRIO_Benchmarking_Example_Code_Guide.doc.

    Thanks,