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HEVC encoder Multi-DSP output binary stream error

JL, Wang
Prodigy 100 points

Hi，

HEVC Encoder (01_00_00_44) works good in a single DSP , but it doesn't work on multiple DSPs as bit stream of the output  looks like  was wrong. The stream can be used as ffmpeg software decoding, but the decoded image is wrong, and the  image which is 0 core decoding is correct, 0~11's image were  wrong (I  used 12 cores to encode the YUV image)

Question1: I doubt when multiple DSPs station, enabled the mailbox moule and other modules, then worng YUV address was transfer to slave cores including core 8, How do I can do?

Question 2, how does the YUV address passed to the master_slave core and slave cores?

Question 3, I have

description ：I have read the similar posts, found that he had LOG, but did not know how the LOG is generated,  the example  LOG is

Fullscreen 6087.console-0-0.log Download 

Start at 2015-03-25 02:42:29  +0100
[2015-03-25 02:42:30] main() on DSP#0 CORE#0
[2015-03-25 02:42:30] Activating core 1
[2015-03-25 02:42:30] Activating core 2
[2015-03-25 02:42:30] Activating core 3
[2015-03-25 02:42:30] Activating core 4
[2015-03-25 02:42:30] Activating core 5
[2015-03-25 02:42:30] Activating core 6
[2015-03-25 02:42:30] Activating core 7
[2015-03-25 02:42:30] Starting IPC
[2015-03-25 02:42:30] IPC: attaching to core#1
[2015-03-25 02:42:30] Attached
[2015-03-25 02:42:30] IPC: attaching to core#2
[2015-03-25 02:42:30] Attached
[2015-03-25 02:42:30] IPC: attaching to core#3
[2015-03-25 02:42:30] Attached
[2015-03-25 02:42:30] IPC: attaching to core#4
[2015-03-25 02:42:30] Attached
[2015-03-25 02:42:30] IPC: attaching to core#5
[2015-03-25 02:42:30] Attached
[2015-03-25 02:42:30] IPC: attaching to core#6
[2015-03-25 02:42:30] Attached
[2015-03-25 02:42:30] IPC: attaching to core#7
[2015-03-25 02:42:30] Attached
[2015-03-25 02:42:30] Starting SYS/BIOS
[2015-03-25 02:42:30] Initialization task @00848318
[2015-03-25 02:42:30] Initializing GateMP
[2015-03-25 02:42:30] L2    free 10f08 of 14810 addr=@00845d00 handle=@00866fa0
[2015-03-25 02:42:30] DDR3  free 39ffff80 of 39ffff80 addr=@86000080 handle=@008460e8
[2015-03-25 02:42:30] DDR3U free ffff80 of ffff80 addr=@85000080 handle=@00846118
[2015-03-25 02:42:30] MSMC  free 24bc80 of 24bc80 addr=@00846000 handle=@008460b8
[2015-03-25 02:42:30] Initializing IPC interrupts
[2015-03-25 02:42:30] Initializing codec interrupts
[2015-03-25 02:42:30] Initializing RMAN
[2015-03-25 02:42:30] Using EDMA3 instance 1
[2015-03-25 02:42:30] Using 12 EDMA channels for codecs and 4 for auxiliary purposes
[2015-03-25 02:42:30] Initializing common support algorithm
[2015-03-25 02:42:30] Initializing statistics component
[2015-03-25 02:42:30] Initializing resize component
[2015-03-25 02:42:30] Initializing transcode queue component
[2015-03-25 02:42:30] Synchronizing cores
[2015-03-25 02:42:30] Commander worker task @0084a1d0
[2015-03-25 02:42:30] Commander task @0084a848
[2015-03-25 02:42:30] Commander worker started
[2015-03-25 02:42:30] Commander task started
[2015-03-25 02:42:30] COMMANDER: Ping 
[2015-03-25 02:42:30] COMMANDER WORKER: Pong 
[2015-03-25 02:42:35] COMMANDER: Creating component #136
[2015-03-25 02:42:35] COMMANDER: Creating component #56
[2015-03-25 02:42:35] Component #56 task @00848338
[2015-03-25 02:42:35] Initializing maser encoder #56 task that runs on 16 cores
[2015-03-25 02:42:35] Create input frame queue "E38" 
[2015-03-25 02:42:35] Initialize video output encoder cyclic buffer: 0x64000000
[2015-03-25 02:42:35] Creating master encoder #56
[2015-03-25 02:42:35] Type: HEVC
[2015-03-25 02:42:35] swbarr name=H265Ebarrier1 user_id=0 num_users=16 user_ids=0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
[2015-03-25 02:42:35] key=@0084e400 barrier value address=@64800240
[2015-03-25 02:42:35] swbarr name=H265Ebarrier2 user_id=0 num_users=16 user_ids=0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
[2015-03-25 02:42:35] key=@0084e418 barrier value address=@64800250
[2015-03-25 02:42:35] swbarr name=H265Ebarrier3 user_id=0 num_users=16 user_ids=0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
[2015-03-25 02:42:35] key=@0084e430 barrier value address=@64800260
[2015-03-25 02:42:35] swbarr name=H265Ebarrier9 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7
[2015-03-25 02:42:35] key=@0084e448 barrier value address=@85000880
[2015-03-25 02:42:35] swbarr name=H265Ebarrier10 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7
[2015-03-25 02:42:35] key=@0084e460 barrier value address=@85000888
[2015-03-25 02:42:35] swbarr name=H265Ebarrier11 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7
[2015-03-25 02:42:35] key=@0084e478 barrier value address=@85000890
[2015-03-25 02:42:35] swbarr name=H265Ebarrier12 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7
[2015-03-25 02:42:35] key=@0084e490 barrier value address=@85000898
[2015-03-25 02:42:35] lock name=H265E_lock100 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7
[2015-03-25 02:42:35] key=@85000980 lock value address=@85000980
[2015-03-25 02:42:35] lock name=H265E_lock200 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7
[2015-03-25 02:42:35] key=@85000a00 lock value address=@85000a00
[2015-03-25 02:42:35] shmem name=shared_mem_pcontext00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=SL2 size=13928 alignment=128
[2015-03-25 02:42:35] key=@0c044a80 shm address=@0c045780 size=13928 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_referenceL000 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=SL2 size=517720 alignment=128
[2015-03-25 02:42:35] key=@0c044a98 shm address=@0c048e00 size=517720 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_NAL_params00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_CACHED size=287486 alignment=128
[2015-03-25 02:42:35] key=@0c044ab0 shm address=@8a027500 size=287486 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_DataSync_params00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_CACHED size=800 alignment=128
[2015-03-25 02:42:35] key=@0c044ac8 shm address=@8a06d800 size=800 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_entry_points00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_CACHED size=228 alignment=128
[2015-03-25 02:42:35] key=@0c044ae0 shm address=@8a06db80 size=228 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_NAL_info00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=SL2 size=3512 alignment=128
[2015-03-25 02:42:35] key=@0c044af8 shm address=@0c0c7480 size=3512 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_bitoutInit00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_CACHED size=24 alignment=128
[2015-03-25 02:42:35] key=@0c044b10 shm address=@8a06dc80 size=24 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_CABAC_Context00 user_id=0 num_users=2 user_ids=0,1 type=DDR_CACHED size=1600 alignment=128
[2015-03-25 02:42:35] key=@0c044b28 shm address=@8a06dd00 size=1600 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_CABAC_Context00 user_id=0 num_users=2 user_ids=0,1 type=DDR_CACHED size=1600 alignment=128
[2015-03-25 02:42:35] key=@0c044b28 shm address=@8a06dd00 size=1600 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_bitout00 user_id=0 num_users=2 user_ids=0,1 type=DDR_CACHED size=24 alignment=128
[2015-03-25 02:42:35] key=@0c044b40 shm address=@8a06e380 size=24 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_bitout00 user_id=0 num_users=2 user_ids=0,1 type=DDR_CACHED size=24 alignment=128
[2015-03-25 02:42:35] key=@0c044b40 shm address=@8a06e380 size=24 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_bitconsumed00 user_id=0 num_users=2 user_ids=0,1 type=DDR_CACHED size=40 alignment=128
[2015-03-25 02:42:35] key=@0c044b58 shm address=@8a06e400 size=40 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_bitconsumed00 user_id=0 num_users=2 user_ids=0,1 type=DDR_CACHED size=40 alignment=128
[2015-03-25 02:42:35] key=@0c044b58 shm address=@8a06e400 size=40 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_CABAC_params00 user_id=0 num_users=2 user_ids=0,1 type=DDR_CACHED size=24 alignment=128
[2015-03-25 02:42:35] key=@0c044b70 shm address=@8a06e480 size=24 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_CABAC_params00 user_id=0 num_users=2 user_ids=0,1 type=DDR_CACHED size=24 alignment=128
[2015-03-25 02:42:35] key=@0c044b70 shm address=@8a06e480 size=24 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_LCU_strs00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=SL2 size=552 alignment=128
[2015-03-25 02:42:35] key=@0c044b88 shm address=@0c0c8280 size=552 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_MV_Buf_loc00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_CACHED size=38808 alignment=128
[2015-03-25 02:42:35] key=@0c044ba0 shm address=@8a06e500 size=38808 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_MV_Buf00 user_id=0 num_users=2 user_ids=0,1 type=DDR_CACHED size=28224 alignment=128
[2015-03-25 02:42:35] key=@0c044bb8 shm address=@8a077d00 size=28224 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_MV_Buf00 user_id=0 num_users=2 user_ids=0,1 type=DDR_CACHED size=28224 alignment=128
[2015-03-25 02:42:35] key=@0c044bb8 shm address=@8a077d00 size=28224 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_const00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=SL2 size=17464 alignment=128
[2015-03-25 02:42:35] key=@0c044bd0 shm address=@0c0c8500 size=17464 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_scan_tables00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_CACHED size=16512 alignment=128
[2015-03-25 02:42:35] key=@0c044be8 shm address=@8a07eb80 size=16512 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_pic_mngmt_str00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_CACHED size=140664 alignment=128
[2015-03-25 02:42:35] key=@0c044c00 shm address=@8a082c00 size=140664 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_ScalingList00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_CACHED size=44520 alignment=128
[2015-03-25 02:42:35] key=@0c044c18 shm address=@8a0a5180 size=44520 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_QPOffsetROI00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=SL2 size=102 alignment=128
[2015-03-25 02:42:35] key=@0c044c30 shm address=@0c0cc980 size=102 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_trans_coeffs00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_CACHED size=1216512 alignment=128
[2015-03-25 02:42:35] key=@0c044c48 shm address=@8a0aff80 size=1216512 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_tmp_bitstream00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_CACHED size=456192 alignment=128
[2015-03-25 02:42:35] key=@0c044c60 shm address=@8a1d8f80 size=456192 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_NAL_info_rmt00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_UNCACHED size=3512 alignment=128
[2015-03-25 02:42:35] key=@0c044c78 shm address=@85000a80 size=5560 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_bitstream00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_CACHED size=456192 alignment=128
[2015-03-25 02:42:35] key=@0c044c90 shm address=@8a248580 size=456192 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_SwappedStream00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_CACHED size=456192 alignment=128
[2015-03-25 02:42:35] key=@0c044ca8 shm address=@8a2b7b80 size=456192 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_chip2chip user_id=0 num_users=2 user_ids=0,8 type=RMT_UNCACHED_NO_LOC size=1152 alignment=128
[2015-03-25 02:42:35] key=@0c044cc0 shm address=@64800280 size=1152 isMultiDsp=1
[2015-03-25 02:42:35] shmem name=shared_recon_stitch_buf user_id=0 num_users=2 user_ids=0,8 type=RMT_UNCACHED_NO_LOC size=446688 alignment=128
[2015-03-25 02:42:35] key=@0c044cd8 shm address=@64800780 size=446688 isMultiDsp=1
[2015-03-25 02:42:35] shmem name=shared_mem_LCU_hdr_loc00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_CACHED size=224928 alignment=128
[2015-03-25 02:42:35] key=@0c044cf0 shm address=@8a327180 size=224928 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_LCU_hdr00 user_id=0 num_users=2 user_ids=0,1 type=DDR_CACHED size=163584 alignment=128
[2015-03-25 02:42:35] key=@0c044d08 shm address=@8a35e080 size=163584 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_LCU_hdr00 user_id=0 num_users=2 user_ids=0,1 type=DDR_CACHED size=163584 alignment=128
[2015-03-25 02:42:35] key=@0c044d08 shm address=@8a35e080 size=163584 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_LCU_hdr_EP00 user_id=0 num_users=2 user_ids=0,1 type=DDR_CACHED size=81792 alignment=128
[2015-03-25 02:42:35] key=@0c044d20 shm address=@8a385f80 size=81792 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_LCU_hdr_EP00 user_id=0 num_users=2 user_ids=0,1 type=DDR_CACHED size=81792 alignment=128
[2015-03-25 02:42:35] key=@0c044d20 shm address=@8a385f80 size=81792 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_LCU_hdr_WF2_loc00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_CACHED size=224928 alignment=128
[2015-03-25 02:42:35] key=@0c044d38 shm address=@8a399f00 size=224928 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_tH265_SAOStr_loc00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_CACHED size=1984 alignment=128
[2015-03-25 02:42:35] key=@0c044d50 shm address=@8a3d0e00 size=1984 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_SAOStr00 user_id=0 num_users=2 user_ids=0,1 type=DDR_CACHED size=184 alignment=128
[2015-03-25 02:42:35] key=@0c044d68 shm address=@8a3d1600 size=184 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_SAOStr00 user_id=0 num_users=2 user_ids=0,1 type=DDR_CACHED size=184 alignment=128
[2015-03-25 02:42:35] key=@0c044d68 shm address=@8a3d1600 size=184 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_CTU_activity00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_CACHED size=139808 alignment=128
[2015-03-25 02:42:35] key=@0c044d80 shm address=@8a3d1700 size=139808 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_chip_activity00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_CACHED size=1056 alignment=128
[2015-03-25 02:42:35] key=@0c044d98 shm address=@8a3f3980 size=1056 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_top_left_recon_loc00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_CACHED size=304128 alignment=128
[2015-03-25 02:42:35] key=@0c044db0 shm address=@8a3f3e00 size=304128 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_dblkd_edge_pixels00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_CACHED size=50688 alignment=128
[2015-03-25 02:42:35] key=@0c044dc8 shm address=@8a43e200 size=50688 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_top_left_recon00 user_id=0 num_users=2 user_ids=0,1 type=DDR_CACHED size=268 alignment=128
[2015-03-25 02:42:35] key=@0c044de0 shm address=@8a44a800 size=268 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_top_left_recon00 user_id=0 num_users=2 user_ids=0,1 type=DDR_CACHED size=268 alignment=128
[2015-03-25 02:42:35] key=@0c044de0 shm address=@8a44a800 size=268 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_slice_tile_no_buf00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_CACHED size=146144 alignment=128
[2015-03-25 02:42:35] key=@0c044df8 shm address=@8a44a980 size=146144 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_RefPic_strs00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=SL2 size=504 alignment=128
[2015-03-25 02:42:35] key=@0c044e10 shm address=@0c0cca00 size=504 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_recon00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_CACHED size=4659480 alignment=128
[2015-03-25 02:42:35] key=@0c044e28 shm address=@8a46e480 size=4659480 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_recon_shared00 user_id=0 num_users=2 user_ids=0,1 type=DDR_CACHED size=366336 alignment=128
[2015-03-25 02:42:35] key=@0c044e40 shm address=@8a8dfe00 size=366336 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_recon_shared00 user_id=0 num_users=2 user_ids=0,1 type=DDR_CACHED size=366336 alignment=128
[2015-03-25 02:42:35] key=@0c044e40 shm address=@8a8dfe00 size=366336 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_dblk_shared00 user_id=0 num_users=2 user_ids=0,1 type=DDR_CACHED size=3456 alignment=128
[2015-03-25 02:42:35] key=@0c044e58 shm address=@8a939500 size=3456 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_dblk_shared00 user_id=0 num_users=2 user_ids=0,1 type=DDR_CACHED size=3456 alignment=128
[2015-03-25 02:42:35] key=@0c044e58 shm address=@8a939500 size=3456 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_SAO_shared00 user_id=0 num_users=2 user_ids=0,1 type=DDR_CACHED size=27648 alignment=128
[2015-03-25 02:42:35] key=@0c044e70 shm address=@8a93a280 size=27648 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_SAO_shared00 user_id=0 num_users=2 user_ids=0,1 type=DDR_CACHED size=27648 alignment=128
[2015-03-25 02:42:35] key=@0c044e70 shm address=@8a93a280 size=27648 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_local_str00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_UNCACHED size=448 alignment=128
[2015-03-25 02:42:35] key=@0c044e88 shm address=@85002080 size=2496 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=EDMA_State_Struct00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=SL2 size=320 alignment=128
[2015-03-25 02:42:35] key=@0c044ea0 shm address=@0c0ccc00 size=320 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_Mode_Decision00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_CACHED size=2055680 alignment=128
[2015-03-25 02:42:35] key=@0c044eb8 shm address=@8a940e80 size=2055680 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_Mode_Decision_Inter00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_CACHED size=104720 alignment=128
[2015-03-25 02:42:35] key=@0c044ed0 shm address=@8ab36c80 size=104720 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_Mode_Decision_Cost00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_CACHED size=448800 alignment=128
[2015-03-25 02:42:35] key=@0c044ee8 shm address=@8ab50600 size=448800 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_SFRC_State00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_UNCACHED size=1272 alignment=128
[2015-03-25 02:42:35] key=@0c044f00 shm address=@85002a80 size=3320 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_Pre_CABAC_Info00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_CACHED size=2717718 alignment=128
[2015-03-25 02:42:35] key=@0c044f18 shm address=@8abbdf80 size=2717718 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_STM00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=RMT_UNCACHED_LOC_SL2 size=2966 alignment=128
[2015-03-25 02:42:35] key=@0c044f30 shm address=@85003780 size=5014 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_EPO_struct00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_CACHED size=4896 alignment=128
[2015-03-25 02:42:35] key=@0c044f48 shm address=@8ae55800 size=4896 isMultiDsp=0
[2015-03-25 02:42:35] shmem name=shared_mem_adptintra_refresh_lcumap00 user_id=0 num_users=8 user_ids=0,1,2,3,4,5,6,7 type=DDR_CACHED size=102 alignment=128
[2015-03-25 02:42:35] key=@0c044f60 shm address=@8ae56b80 size=102 isMultiDsp=0
[2015-03-25 02:42:35] swbarr name=H265Ebarrier4 user_id=0 num_users=2 user_ids=0,8
[2015-03-25 02:42:35] key=@0084e4a8 barrier value address=@6486d870
[2015-03-25 02:42:35] swbarr name=H265Ebarrier5 user_id=0 num_users=2 user_ids=0,8
[2015-03-25 02:42:35] key=@0084e4c0 barrier value address=@6486d880
[2015-03-25 02:42:35] swbarr name=H265Ebarrier6 user_id=0 num_users=2 user_ids=0,8
[2015-03-25 02:42:35] key=@0084e4d8 barrier value address=@6486d890
[2015-03-25 02:42:35] swbarr name=H265Ebarrier7 user_id=0 num_users=2 user_ids=0,8
[2015-03-25 02:42:35] key=@0084e4f0 barrier value address=@6486d8a0
[2015-03-25 02:42:35] swbarr name=H265Ebarrier8 user_id=0 num_users=2 user_ids=0,8
[2015-03-25 02:42:35] key=@0084e508 barrier value address=@6486d8b0
[2015-03-25 02:42:35] swbarr name=H265Ebarrier9 user_id=0 num_users=2 user_ids=0,8
[2015-03-25 02:42:35] key=@0084e520 barrier value address=@6486d8c0
[2015-03-25 02:42:35] swbarr name=H265Ebarrier10 user_id=0 num_users=2 user_ids=0,8
[2015-03-25 02:42:35] key=@0084e538 barrier value address=@6486d8d0
[2015-03-25 02:42:35] Create encoder buffers
[2015-03-25 02:42:35] minNumInBufs 3
[2015-03-25 02:42:35] minNumOutBufs 1
[2015-03-25 02:42:35] minInBufSize[0] 405504 0
[2015-03-25 02:42:35] minInBufSize[1] 101376 0
[2015-03-25 02:42:35] minInBufSize[2] 101376 0
[2015-03-25 02:42:35] minOutBufSize[0] 456192 0
[2015-03-25 02:42:35] Connecting encoder input #56 to output #136 
[2015-03-25 02:42:35] Master encoder #56 initialized 704x576@25p


If My analysis is wrong, there is any othee reasons  to make a series of code stream is wrong, the results bit streaming isas follows

stream.cut.123

Regards,

JL,wang

  • 0
    TI__Guru* 81335 points

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please read all the links below my signature.

    We will get back to you on the above query shortly. Thank you for your patience.

  • 0
    TI__Guru* 81335 points
    What is the DSP and Board used? Please provide the DSP part number and board information. Thank you.
  • 0 in reply to Raja
    Prodigy 100 points

    Hi,Raja:

    The  DSP is C6678, the board has two chips

    Regards

    Thanks

    JL,Wang

  • 0
    Expert 1230 points
    Hi JL,wang

    Please find the answers to the queries below

    1. Regarding Input YUV, host copies the input yuv to DDR memory of the all shannon chips.
    2. In Single chip, as input YUV data is in DDR, the input YUV is visible to all the cores.
    3. Can you please let us know the mcsdk version you are using as host application, as dumping of log information depends on host application.

    It looks like you are using the older version of encoder libray, can you please try with the latest version (02.00.00.02) of encoder library from the below link.
    software-dl.ti.com/.../index_FDS.html

    From the message it looks like are you are able to encode the stream on single core and you are facing issues with encoding on multichip. Can you please let us know if you are able to encode in single chip. ((0 - 7) cores)
    Please share the config you are using, so that we can try to encode at our end.

    Thanks and Regards,
    Palachandra M V
  • 0 in reply to Palachandra Venkataraju
    Prodigy 100 points
    Hi, Palachandra M V
    1, I tried with the latest version(02.00.00.02) few months ago. But it may be unstabler for rate control than tne version(01.00.00.44). Then I still use the version(01.00.00.44) now.
    2, In Single chip, I am able to encode with cores(0~7), and the output bit stream is right. As you said I am facing issues with encoding on multichip. In multi_chips, the encode lib can works, but the output bit stream is wrong as above I post.
    3, I didn't use any version of the mcsdk as host application. In my code, I have written the YUV data(YUV420P) to the chip0(for example,the address is 0x90000000), and I copy the YUV data to the same address of chip1(memcopy to the address 0x90000000 of chip1), and I can see the right Image in the address(0x90000000) of chip0 and chip1's DDR3.
    4, I want to know how the YUV address was transfer to slave cores(8~11)? In multichips, why the cores(1~7) can't recieve right YUV data?

    Regards
    Thanks
    JL,Wang
  • 0 in reply to JL, Wang
    Expert 1230 points
    JL,wang

    Please find my reply inline:

    [Query 1] : I tried with the latest version(02.00.00.02) few months ago. But it may be unstabler for rate control than tne version(01.00.00.44). Then I still use the version(01.00.00.44) now.
    [Palachandra]
    - Can you please check whether you are facing similar issues (stream corruption in multichip) with the latest version(02.00.00.02) of encoder library.

    [Query 3] : I didn't use any version of the mcsdk as host application. In my code, I have written the YUV data(YUV420P) to the chip0(for example,the address is 0x90000000), and I copy the YUV data to the same address of chip1(memcopy to the address 0x90000000 of chip1), and I can see the right Image in the address(0x90000000) of chip0 and chip1's DDR3.
    [Palachandra]
    - Since you are not using TI's mcsdk as the host, have you written you own host application?

    [Query 4] : I want to know how the YUV address was transfer to slave cores(8~11)? In multichips, why the cores(1~7) can't recieve right YUV data?
    [Palachandra]
    In our setup, mcsdk host application copies input YUV data to DDR of indvidual chips, since DDR is shared accross all cores in a chip, input yuv data is available for all the cores in the chip.

    To check the reason for stream corruption can you please share us the
    - Config file you are using.
    - Single chip Encoded stream.
    - If possible first few frames of input yuv
    So that we can try to encode the same at our end.


    Thanks and Regards,
    Palachandra
  • 0 in reply to Palachandra Venkataraju
    Prodigy 100 points

    Hi, Palachandra

    1, I'm sure it has similar issues with the latest version(02.00.00.02), In MCSDK Video(mcsdk_video_2_2_0_45), the version(01.00.00.44) was used and it works without any issues such as stream corruption in multichips.

    2, I do written my own host application. The purpose of host application is to provide YUV data to the two chips of C6678 in same address of their  local DDR.

    3, I know that input yuv data is available for all the cores in the chip, but only the core0's Inputbuffer and Outbutbuffer were assigned the YUV address. So I want to know the YUV address was transfer to the other cores. Is the buffers of (1~11) cores do not need  to be assigned the address of YUV data?

    4,The config of my application is following

    Fullscreen 3823.config.txt Download 
    #ifdef test
	gConfig->framesToEncode = 100;
#endif
	//
	gConfig->ncores = 10;
	gConfig->maxIntraFrameInterval = 90;
	gConfig->maxNumRefFrames = 1;
	gConfig->enableWPP = 0;
	gConfig->enableVirtualTile = 0;
	gConfig->disableVirtualTileDependency = 1;
	gConfig->videnc2Params.outputDataMode = 3;
	gConfig->videnc2Params.numOutputDataUnits = 1;
	gConfig->DynamicParams.videnc2DynamicParams.generateHeader = 0;
	gConfig->DynamicParams.videnc2DynamicParams.mvAccuracy = 2;
	gConfig->DynamicParams.videnc2DynamicParams.sampleAspectRatioHeight = 1;
	gConfig->DynamicParams.videnc2DynamicParams.sampleAspectRatioWidth  = 1;
	gConfig->ctbCodingParams.maxCTBSize = 64;
	gConfig->ctbCodingParams.maxCUDepth = 3;
	gConfig->enableTransQuantBypass = 0;
	gConfig->enableTransformSkip = 0;
	gConfig->enableROI = 0;
	//gConfig->DynamicParams.videnc2DynamicParams.inputWidth = 1280;
	//gConfig->DynamicParams.videnc2DynamicParams.inputHeight = 720;
	gConfig->DynamicParams.videnc2DynamicParams.targetBitRate = 1500000;
	gConfig->DynamicParams.videnc2DynamicParams.targetFrameRate = 25000;
	gConfig->DynamicParams.videnc2DynamicParams.intraFrameInterval = 75;
	gConfig->DynamicParams.videnc2DynamicParams.interFrameInterval = 3;
	gConfig->scalingMatrixPreset = 0;
	gConfig->enablSEI = 0;
	gConfig->decRefreshType = 0;
	gConfig->decRefreshInterval = 1;//if 0,would not be decode!
	gConfig->videnc2Params.encodingPreset = XDM_HIGH_SPEED;
	gConfig->videnc2Params.profile = 1;
	gConfig->videnc2Params.level = 41;
	gConfig->videnc2Params.maxInterFrameInterval = 3;
	gConfig->interCodingParams.enableTmvp = 0;
	gConfig->interCodingParams.interCodingBias = 0;
	gConfig->interCodingParams.skipMVCodingBias = 0;
	gConfig->videnc2Params.rateControlPreset = IVIDEO_LOW_DELAY;

	/* rateControlParams */
	gConfig->rateControlParams.rateControlParamsPreset = IH265_RATECONTROLPARAMS_USERDEFINED;
	gConfig->rateControlParams.enableHRDComplianceMode = 0;
	gConfig->rateControlParams.qualityFactorIP = 0;
	gConfig->rateControlParams.initialBufferLevel = 2000000;
	gConfig->rateControlParams.hrdBufferSize = 2000000;
	gConfig->rateControlParams.rcAlgo = IH265_RATECONTROL_CBR;
	gConfig->rateControlParams.qpI = 25;
	gConfig->rateControlParams.qpP = 25;
	gConfig->rateControlParams.qpMaxI = 51;
	gConfig->rateControlParams.qpMinI = 20;
	gConfig->rateControlParams.qpMaxP = 51;
	gConfig->rateControlParams.qpMinP = 20;
	gConfig->rateControlParams.qpMaxB = 51;
	gConfig->rateControlParams.qpMinB = 20;
	gConfig->rateControlParams.qpOffsetB = 2;
	gConfig->rateControlParams.cbQPIndexOffset = 0;
	gConfig->rateControlParams.crQPIndexOffset = 0;
	gConfig->rateControlParams.enableFrameSkip = 0;
	gConfig->rateControlParams.enablePartialFrameSkip = 1;
	gConfig->rateControlParams.maxFrameSkipCnt = 0;
	gConfig->rateControlParams.maxDeltaQP = -5;
	gConfig->rateControlParams.SubFrameRC = 0;//the not support
	gConfig->rateControlParams.enablePRC = 0;

	gConfig->enableTransQuantBypass = 0;
	gConfig->loopFilterParams.separateCbCrSAO = 0;//??
	gConfig->loopFilterParams.enableDeblockFilter = 1;
	gConfig->loopFilterParams.offsetDeblockBetaDiv2 = 0;
	gConfig->loopFilterParams.offsetDeblockTcDiv2 = 0;
	gConfig->loopFilterParams.offsetLoopFilterInPPSFlag =0;
	gConfig->loopFilterParams.loopFilterParamsPreset = 0;
	gConfig->maxPoc = 32;//??
	gConfig->enableTransformSkip = 0;
	gConfig->loopFilterParams.enableLoopFilterSliceBoundary = 0;
	gConfig->loopFilterParams.enableSaoFilter = 2;
	gConfig->sliceCodingParams.sliceCodingPreset = 0;
	gConfig->sliceCodingParams.sliceCodingMode = 1;
	gConfig->sliceCodingParams.sliceCodingArg = 0;
	gConfig->sliceCodingParams.enableDependentSlice = 1;
	gConfig->sliceCodingParams.enableTiles = 1;
	gConfig->sliceCodingParams.numTileColumns = 2;
	gConfig->sliceCodingParams.numTileRows = 2;
	gConfig->loopFilterParams.enableLoopFilterTileBoundary = 0;
	gConfig->interCodingParams.interCodingPreset = 1;
	gConfig->interCodingParams.numMergeCandidates = 5;
	gConfig->interCodingParams.enableBiPredMode = 1;
	gConfig->interCodingParams.searchRangeHorP = 144;
	gConfig->interCodingParams.searchRangeVerP = 128;
	gConfig->interCodingParams.searchRangeHorB = 144;
	gConfig->interCodingParams.searchRangeVerB = 128;
	gConfig->interCodingParams.enableFastIntraAlgo = 1;//
	gConfig->vuiCodingParams.vuiCodingPreset = 0;
	gConfig->enableVui = 0;
	gConfig->vuiCodingParams.hrdParamsPresentFlag = 0;
	gConfig->vuiCodingParams.frame_field_info_present_flag = 0;
	gConfig->vuiCodingParams.aspectRatioInfoPresentFlag = 0;
	gConfig->vuiCodingParams.aspectRatioIdc = 0;
	gConfig->vuiCodingParams.colourDescriptionPresentFlag = 0;
	gConfig->vuiCodingParams.colourPrimaries = 0;
	gConfig->vuiCodingParams.matrixCoefficients = 0;
	gConfig->vuiCodingParams.timingInfoPresentFlag = 0;
	gConfig->vuiCodingParams.transferCharacteristics = 0;
	gConfig->vuiCodingParams.videoFormat = 0;
	gConfig->vuiCodingParams.videoFullRangeFlag = 0;
	gConfig->vuiCodingParams.videoSignalTypePresentFlag = 0;
	gConfig->debugTraceLevel = 0;
	gConfig->lastNFramesToLog = 0;
	gConfig->gopCntrlParams.gopCntrlParamsPreset = IH265_GOPCTRLPRESET_DEFAULT;

	gConfig->intraCodingParams.intraCodingPreset = IH265_INTRACODINGPRESET_USERDEFINED;//1
	gConfig->intraCodingParams.intraRefreshRate = 0;//IH265_INTRAREFRESH_DEFAULT;
	gConfig->intraCodingParams.intraRefreshMethod = IH265_INTRAREFRESH_DEFAULT;//0
	gConfig->intraCodingParams.enableStrongIntraSmoothing = 1;
	gConfig->intraCodingParams.constrainedIntraPredEnable = 0;

    5, Single chip Encoded stream is following

    265.123

    6, The YUV data was generated by host application, not always the same one.

    7, My stream of the corruption is following as post yesterday

    8357.stream.cut.123

    Why can the corruption stream was generated?

    Thanks and Regards,
    JL,Wang

  • 0 in reply to JL, Wang
    Expert 1230 points

    Hi JL,Wang

    1. I am unable to decode the attached single chip output stream (265.123), Is there any corruption observed in single chip output also.

    2. To encode a stream on multichip host will manage the below requirements
    - Copying of Input YUV data to DDR of each chip.
    - There are 3 ways by which interchip communication is carried out
        - Host allocates shared memory region (x86 memory), which is visible to all the chips and communication is carried through PCIe.
        - A part of the DDR is allocated as interchip memory which can used for data transfers between adjacent chips.
        - Mailbox are used and interupts are associated with mailbox.

    In addition to the above
    - MCSDK memory manager is used to manage input and output memory requirements
    - Inside our codec we have memory mappings for Cached DDR, Uncached DDR, Host memory shared to DSPs.

    Please check whether your host application supports following requirements.

    For more information please refer to the below link:
    processors.wiki.ti.com/.../MCSDK_VIDEO_2.x_Development_Guide
    processors.wiki.ti.com/.../Desktop-linux-sdk_01.00.00_Development_Guide

    Thanks and Regards,
    Palachandra M V

  • 0 in reply to Palachandra Venkataraju
    Prodigy 100 points

    Hi， Palachandra M V

    1, Before I post the stream(265.123 )is ts-stream which can be opened by VLC, and corresponding the es-stream is following :
    7853.stream_8cores.123

    Corresponding， the multi-chip station， the bit stream is :

    3252.stream_multichip.123
    2, I have checked the  3 ways interchip communication, and did not find any problems. Explain that I did not use PCIe for inter-chip communication， rather than I use the MPAX and  hyperlink moudle to map a Virtual PCIe because my  board  not  PCIe to ARM(or x86). I mapped as following

        chip0                                                                               chip1

    0xF20000000                                                               0xF2000000

    mpax mapping to                                                        mpax mapping to

    0x82000000                                                                 0x42000000

                                                                                            hyperlink maping to

                                                                                           chip0's  0x82000000

    So for two chips,  from the same address 0xF2000000 will mapped the same address of chip0's 0x82000000, by this why to instead the PCIe space. Can you unstand me ?  Will it generate any error In this way?

    And "A part of the DDR is allocated as interchip memory which can used for data transfers between adjacent chips" as you said, I had used the Hyperlink for the adjacent chips communication.

    A part of code and the .map file are :


    enc_app_map.txt

    Fullscreen code.txt Download 
    static XDAS_Int32 create_shm_key(Key_t *key, XDAS_Int32 user_idx, IVIDMC3_ShMemCfg_t *cfg)
{
  XDAS_Int32  ret = 0;
  /* Copy configuration parameters. */
  key->mem_size      = cfg->size;
  key->mem_align     = cfg->alignment;
  key->mem_attr      = cfg->attr;
  /*  
   *  If number of chips involved is 2, try to obtain a buffer which is directly 
   *  mapped between both chips.
   */
  if ( key->num_chips == 2 && key->mem_attr != IVIDMC3_SHMEM_ATTRS_RMT_UNCACHED_NO_LOC )
  {
    Heap_t      *rmt_heap, *loc_heap;
    XDAS_UInt32           loc_chip_id, rmt_chip_id, heap_size;
    XDAS_Int32            i;
    XDAS_UInt8           *loc_shm_ptr = NULL, *rmt_shm_ptr = NULL, *heap_base;
    XDAS_UInt8 			 allocatedHLMem = 0;
	
    /* Find out whether region is cached or uncached. */
    switch ( key->mem_attr )
    {
      case IVIDMC3_SHMEM_ATTRS_SL2:
      case IVIDMC3_SHMEM_ATTRS_DDR_CACHED:
      case IVIDMC3_SHMEM_ATTRS_RMT_CACHED_LOC_DDR:
      case IVIDMC3_SHMEM_ATTRS_RMT_CACHED_LOC_SL2:
	    if(useHyperLink)
		{
			loc_heap   = &c2c_cached_shmHLHeap;
			heap_base  = c2c_cached_shmHL_mem;
			heap_size  = c2c_cached_shmHL_MEM_SIZE;
			allocatedHLMem = 1;
		}
            break;		
      case IVIDMC3_SHMEM_ATTRS_DDR_UNCACHED:
      case IVIDMC3_SHMEM_ATTRS_RMT_UNCACHED_LOC_DDR:
      case IVIDMC3_SHMEM_ATTRS_RMT_UNCACHED_LOC_SL2:
      case IVIDMC3_SHMEM_ATTRS_RMT_UNCACHED_NO_LOC:
        loc_heap   = &c2c_uncached_shmHeap;
        heap_base  = c2c_uncached_shm_mem;
        heap_size  = c2c_uncached_shm_MEM_SIZE;
        break;
    }
    /* Get local chip ID */
    loc_chip_id = SIUVID_MC_MULTICHIP_DSP_NUM(key->core_ids[user_idx]);

    /* Find the remote chip ID */
    for ( i = 0; i < key->num_cores; i++ )
    {
      if ( loc_chip_id != SIUVID_MC_MULTICHIP_DSP_NUM(key->core_ids[i]) )
      {
        rmt_chip_id = SIUVID_MC_MULTICHIP_DSP_NUM(key->core_ids[i]);
        break;
      }
    }
	}	
    /* 
     *  Check if the entire local C2C cached heap is available to the remote chip, 
     *  or if the entire remote C2C cached heap is available to the local chip. 
     */
    if ( (siuVidMc3_C2C_mapping(loc_heap, loc_chip_id, rmt_chip_id) != NULL) &&
         (siuVidMc3_C2C_mapping(heap_base, loc_chip_id, rmt_chip_id) != NULL) &&
         (siuVidMc3_C2C_mapping(&heap_base[heap_size - 1], loc_chip_id, rmt_chip_id) != NULL) )
    {
      /* Allocate memory from local heap */
      loc_shm_ptr = siuVidMc3_alloc(key->mem_size, key->mem_align, loc_heap);
      rmt_shm_ptr = siuVidMc3_C2C_mapping( loc_shm_ptr, loc_chip_id, rmt_chip_id);
    }
    else if ( ((rmt_heap = siuVidMc3_C2C_mapping(loc_heap, rmt_chip_id, loc_chip_id)) != NULL) &&
              (siuVidMc3_C2C_mapping(heap_base, rmt_chip_id, loc_chip_id) != NULL) &&
              (siuVidMc3_C2C_mapping(&heap_base[heap_size - 1], rmt_chip_id, loc_chip_id) != NULL) )

    {
      /* Allocate memory from the remote heap */
      rmt_shm_ptr = siuVidMc3_alloc(key->mem_size, key->mem_align, rmt_heap);
      loc_shm_ptr = siuVidMc3_C2C_mapping( rmt_shm_ptr, rmt_chip_id, loc_chip_id);
    }

    if ( (rmt_shm_ptr != NULL) && (rmt_shm_ptr != NULL) )
    {
      /* Assign shm_ptrs to the key */
      for ( i = 0; i < key->num_cores; i++)
      {
        if ( loc_chip_id == SIUVID_MC_MULTICHIP_DSP_NUM(key->core_ids[i]) )
          key->loc_mem[i] = loc_shm_ptr;
        else if ( rmt_chip_id == SIUVID_MC_MULTICHIP_DSP_NUM(key->core_ids[i]) )
          key->loc_mem[i] = rmt_shm_ptr;
      }
    }
  }
 /*Comment
  *for example ,rmt_shm_ptr == 0x44000000, 
  *             loc_shm_ptr == 0x84000000
  */

    Is there any other reasons for the multichip corruption stream?(especially DMA transfer?)

    Thanks and Regards,

    JL, Wang

  • 0 in reply to JL, Wang
    Expert 1230 points

    Hi JL, Wang,

    1. Can you please let us know the interface between host and individual dsp, how many lanes are provided.

    2. As single chip is working fine on chip 0, to confirm functionality on chip 1, can you please check whether is it possible to encode the stream on chip1 independently (Single chip mode).

    3. When tile is enabled inter chip communication is minimal, can you please check whether you able to encode stream when tile is enabled. I have attached the config for enabling tiles. (Please try encoding on both single chip and multi chip by enabling tiles)

    4. To dig more into the issue can you please give information regarding address and size of shared memory with respect to key index. (Please add  printf in keycreate functions).

    Thanks and Regards,
    Palachandra M V

    Fullscreen config_enable_tiles.txt Download 
    #ifdef test
	gConfig->framesToEncode = 100;
#endif
	//
	gConfig->ncores = 10;
	gConfig->maxIntraFrameInterval = 90;
	gConfig->maxNumRefFrames = 1;
	gConfig->enableWPP = 0;
	gConfig->enableVirtualTile = 0;
	gConfig->disableVirtualTileDependency = 1;
	gConfig->videnc2Params.outputDataMode = 3;
	gConfig->videnc2Params.numOutputDataUnits = 1;
	gConfig->DynamicParams.videnc2DynamicParams.generateHeader = 0;
	gConfig->DynamicParams.videnc2DynamicParams.mvAccuracy = 2;
	gConfig->DynamicParams.videnc2DynamicParams.sampleAspectRatioHeight = 1;
	gConfig->DynamicParams.videnc2DynamicParams.sampleAspectRatioWidth  = 1;
	gConfig->ctbCodingParams.maxCTBSize = 64;
	gConfig->ctbCodingParams.maxCUDepth = 3;
	gConfig->enableTransQuantBypass = 0;
	gConfig->enableTransformSkip = 0;
	gConfig->enableROI = 0;
	//gConfig->DynamicParams.videnc2DynamicParams.inputWidth = 1280;
	//gConfig->DynamicParams.videnc2DynamicParams.inputHeight = 720;
	gConfig->DynamicParams.videnc2DynamicParams.targetBitRate = 1500000;
	gConfig->DynamicParams.videnc2DynamicParams.targetFrameRate = 25000;
	gConfig->DynamicParams.videnc2DynamicParams.intraFrameInterval = 75;
	gConfig->DynamicParams.videnc2DynamicParams.interFrameInterval = 3;
	gConfig->scalingMatrixPreset = 0;
	gConfig->enablSEI = 0;
	gConfig->decRefreshType = 0;
	gConfig->decRefreshInterval = 1;//if 0,would not be decode!
	gConfig->videnc2Params.encodingPreset = XDM_HIGH_SPEED;
	gConfig->videnc2Params.profile = 1;
	gConfig->videnc2Params.level = 41;
	gConfig->videnc2Params.maxInterFrameInterval = 3;
	gConfig->interCodingParams.enableTmvp = 0;
	gConfig->interCodingParams.interCodingBias = 0;
	gConfig->interCodingParams.skipMVCodingBias = 0;
	gConfig->videnc2Params.rateControlPreset = IVIDEO_LOW_DELAY;

	/* rateControlParams */
	gConfig->rateControlParams.rateControlParamsPreset = IH265_RATECONTROLPARAMS_USERDEFINED;
	gConfig->rateControlParams.enableHRDComplianceMode = 0;
	gConfig->rateControlParams.qualityFactorIP = 0;
	gConfig->rateControlParams.initialBufferLevel = 2000000;
	gConfig->rateControlParams.hrdBufferSize = 2000000;
	gConfig->rateControlParams.rcAlgo = IH265_RATECONTROL_CBR;
	gConfig->rateControlParams.qpI = 25;
	gConfig->rateControlParams.qpP = 25;
	gConfig->rateControlParams.qpMaxI = 51;
	gConfig->rateControlParams.qpMinI = 20;
	gConfig->rateControlParams.qpMaxP = 51;
	gConfig->rateControlParams.qpMinP = 20;
	gConfig->rateControlParams.qpMaxB = 51;
	gConfig->rateControlParams.qpMinB = 20;
	gConfig->rateControlParams.qpOffsetB = 2;
	gConfig->rateControlParams.cbQPIndexOffset = 0;
	gConfig->rateControlParams.crQPIndexOffset = 0;
	gConfig->rateControlParams.enableFrameSkip = 0;
	gConfig->rateControlParams.enablePartialFrameSkip = 1;
	gConfig->rateControlParams.maxFrameSkipCnt = 0;
	gConfig->rateControlParams.maxDeltaQP = -5;
	gConfig->rateControlParams.SubFrameRC = 0;//the not support
	gConfig->rateControlParams.enablePRC = 0;

	gConfig->enableTransQuantBypass = 0;
	gConfig->loopFilterParams.separateCbCrSAO = 0;//??
	gConfig->loopFilterParams.enableDeblockFilter = 1;
	gConfig->loopFilterParams.offsetDeblockBetaDiv2 = 0;
	gConfig->loopFilterParams.offsetDeblockTcDiv2 = 0;
	gConfig->loopFilterParams.offsetLoopFilterInPPSFlag =0;
	gConfig->loopFilterParams.loopFilterParamsPreset = 0;
	gConfig->maxPoc = 32;//??
	gConfig->enableTransformSkip = 0;
	gConfig->loopFilterParams.enableLoopFilterSliceBoundary = 0;
	gConfig->loopFilterParams.enableSaoFilter = 2;
	gConfig->sliceCodingParams.sliceCodingPreset = 1;
	gConfig->sliceCodingParams.sliceCodingMode = 0;
	gConfig->sliceCodingParams.sliceCodingArg = 0;
	gConfig->sliceCodingParams.enableDependentSlice = 0;
	gConfig->sliceCodingParams.enableTiles = 1;
	gConfig->sliceCodingParams.numTileColumns = 1;
	gConfig->sliceCodingParams.numTileRows = 2;
	gConfig->loopFilterParams.enableLoopFilterTileBoundary = 0;
	gConfig->interCodingParams.interCodingPreset = 1;
	gConfig->interCodingParams.numMergeCandidates = 5;
	gConfig->interCodingParams.enableBiPredMode = 1;
	gConfig->interCodingParams.searchRangeHorP = 144;
	gConfig->interCodingParams.searchRangeVerP = 128;
	gConfig->interCodingParams.searchRangeHorB = 144;
	gConfig->interCodingParams.searchRangeVerB = 128;
	gConfig->interCodingParams.enableFastIntraAlgo = 1;//
	gConfig->vuiCodingParams.vuiCodingPreset = 0;
	gConfig->enableVui = 0;
	gConfig->vuiCodingParams.hrdParamsPresentFlag = 0;
	gConfig->vuiCodingParams.frame_field_info_present_flag = 0;
	gConfig->vuiCodingParams.aspectRatioInfoPresentFlag = 0;
	gConfig->vuiCodingParams.aspectRatioIdc = 0;
	gConfig->vuiCodingParams.colourDescriptionPresentFlag = 0;
	gConfig->vuiCodingParams.colourPrimaries = 0;
	gConfig->vuiCodingParams.matrixCoefficients = 0;
	gConfig->vuiCodingParams.timingInfoPresentFlag = 0;
	gConfig->vuiCodingParams.transferCharacteristics = 0;
	gConfig->vuiCodingParams.videoFormat = 0;
	gConfig->vuiCodingParams.videoFullRangeFlag = 0;
	gConfig->vuiCodingParams.videoSignalTypePresentFlag = 0;
	gConfig->debugTraceLevel = 0;
	gConfig->lastNFramesToLog = 0;
	gConfig->gopCntrlParams.gopCntrlParamsPreset = IH265_GOPCTRLPRESET_DEFAULT;

	gConfig->intraCodingParams.intraCodingPreset = IH265_INTRACODINGPRESET_USERDEFINED;//1
	gConfig->intraCodingParams.intraRefreshRate = 0;//IH265_INTRAREFRESH_DEFAULT;
	gConfig->intraCodingParams.intraRefreshMethod = IH265_INTRAREFRESH_DEFAULT;//0
	gConfig->intraCodingParams.enableStrongIntraSmoothing = 1;
	gConfig->intraCodingParams.constrainedIntraPredEnable = 0;

  • 0 in reply to Palachandra Venkataraju
    Prodigy 100 points

    Hi, Palachandra M V

    1, There are two lanes are provided, and ARM was connected the chip0 dsp(C6678 chip0) with PCIe, then ARM unconnect the chip1 dsp(C6678 chip1) with any hardware. The two chips of C6678 were connected each other with the Hyperlink moudle. So if ARM will communicate with the chip1 dsp, it must be access the chip0 dsp which access the chip1 through the Hyperlink.

    If the two chips dsp will share a part of memory for inter-chip communication, I instead the PCIe space by the following way (I have posted before)

    "2, I have checked the  3 ways interchip communication, and did not find any problems. Explain that I did not use PCIe for inter-chip communication， rather than I use the MPAX and  hyperlink moudle to map a Virtual PCIe because my  board  not  PCIe to ARM(or x86). I mapped as following

        chip0                                                                               chip1

    0xF20000000                                                               0xF2000000

    mpax mapping to                                                        mpax mapping to

    0x82000000                                                                 0x42000000

                                                                                            hyperlink maping to

                                                                                           chip0's  0x82000000

    So for two chips,  from the same address 0xF2000000 will mapped the same address of chip0's 0x82000000, by this why to instead the PCIe space. Can you unstand me ?  Will it generate any error In this way?"

    2, Due to hardware restrictions, I didn't checked the "check whether is it possible to encode the stream on chip1 independently (Single chip mode).",  I will check it tomorrow.

    3, For"To dig more into the issue can you please give information regarding address and size of shared memory with respect to key index. (Please add  printf in keycreate functions).",  I had added the printf in the keycreate functions, and copy the LOG as a .txt file as following :

    Fullscreen 7356.LOG.txt Download 
    [C66xx_8] shmem name =  barrier syncPoint12  user_id = 8 num_users = 2 user_ids = 0 8 shmem name =  barrier syncPoint14  user_id = 8 num_users = 2 user_ids = 0 8 shmem name =  barrier syncPoint16  user_id = 8 num_users = 2 user_ids = 0 8 shmem name =  barrier syncPo
[C66xx_0] shmem name =  barrier syncPoint12  user_id = 0 num_users = 2 user_ids = 0 8 shmem name =  barrier syncPoint14  user_id = 0 num_users = 2 user_ids = 0 8 shmem name =  barrier syncPoint16  user_id = 0 num_users = 2 user_ids = 0 8 shmem name =  barrier syncPo
[C66xx_1] shmem name =  barrier syncPoint13  user_id = 1 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  barrier syncPoint15  user_id = 1 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  barrier syncPoint17  user_id = 1 num_users = 8 user_ids = 0 1 2 3 
[C66xx_2] shmem name =  barrier syncPoint13  user_id = 2 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  barrier syncPoint15  user_id = 2 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  barrier syncPoint17  user_id = 2 num_users = 8 user_ids = 0 1 2 3 
[C66xx_3] shmem name =  barrier syncPoint13  user_id = 3 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  barrier syncPoint15  user_id = 3 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  barrier syncPoint17  user_id = 3 num_users = 8 user_ids = 0 1 2 3 
[C66xx_4] shmem name =  barrier syncPoint13  user_id = 4 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  barrier syncPoint15  user_id = 4 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  barrier syncPoint17  user_id = 4 num_users = 8 user_ids = 0 1 2 3 
[C66xx_5] shmem name =  barrier syncPoint13  user_id = 5 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  barrier syncPoint15  user_id = 5 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  barrier syncPoint17  user_id = 5 num_users = 8 user_ids = 0 1 2 3 
[C66xx_6] shmem name =  barrier syncPoint13  user_id = 6 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  barrier syncPoint15  user_id = 6 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  barrier syncPoint17  user_id = 6 num_users = 8 user_ids = 0 1 2 3 
[C66xx_7] shmem name =  barrier syncPoint13  user_id = 7 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  barrier syncPoint15  user_id = 7 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  barrier syncPoint17  user_id = 7 num_users = 8 user_ids = 0 1 2 3 
[C66xx_7] 4 5 6 7 shmem name =  H265Ebarrier1  user_id = 7 num_users = 10 user_ids = 0 1 2 3 4 5 6 7 8 9 shmem name =  H265Ebarrier2  user_id = 7 num_users = 10 user_ids = 0 1 2 3 4 5 6 7 8 9 shmem name =  H265Ebarrier3  user_id = 7 num_users = 10 user_ids = 0 1 2 3
[C66xx_7]  4 5 6 7 8 9 shmem name =  H265Ebarrier8  user_id = 7 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265Ebarrier9  user_id = 7 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265Ebarrier10  user_id = 7 num_users = 8 user_ids = 0 1 2 3 4 5 
[C66xx_0] int13  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  barrier syncPoint15  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  barrier syncPoint17  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265Eb
[C66xx_1] 4 5 6 7 shmem name =  H265Ebarrier1  user_id = 1 num_users = 10 user_ids = 0 1 2 3 4 5 6 7 8 9 shmem name =  H265Ebarrier2  user_id = 1 num_users = 10 user_ids = 0 1 2 3 4 5 6 7 8 9 shmem name =  H265Ebarrier3  user_id = 1 num_users = 10 user_ids = 0 1 2 3
[C66xx_2] 4 5 6 7 shmem name =  H265Ebarrier1  user_id = 2 num_users = 10 user_ids = 0 1 2 3 4 5 6 7 8 9 shmem name =  H265Ebarrier2  user_id = 2 num_users = 10 user_ids = 0 1 2 3 4 5 6 7 8 9 shmem name =  H265Ebarrier3  user_id = 2 num_users = 10 user_ids = 0 1 2 3
[C66xx_3] 4 5 6 7 shmem name =  H265Ebarrier1  user_id = 3 num_users = 10 user_ids = 0 1 2 3 4 5 6 7 8 9 shmem name =  H265Ebarrier2  user_id = 3 num_users = 10 user_ids = 0 1 2 3 4 5 6 7 8 9 shmem name =  H265Ebarrier3  user_id = 3 num_users = 10 user_ids = 0 1 2 3
[C66xx_4] 4 5 6 7 shmem name =  H265Ebarrier1  user_id = 4 num_users = 10 user_ids = 0 1 2 3 4 5 6 7 8 9 shmem name =  H265Ebarrier2  user_id = 4 num_users = 10 user_ids = 0 1 2 3 4 5 6 7 8 9 shmem name =  H265Ebarrier3  user_id = 4 num_users = 10 user_ids = 0 1 2 3
[C66xx_5] 4 5 6 7 shmem name =  H265Ebarrier1  user_id = 5 num_users = 10 user_ids = 0 1 2 3 4 5 6 7 8 9 shmem name =  H265Ebarrier2  user_id = 5 num_users = 10 user_ids = 0 1 2 3 4 5 6 7 8 9 shmem name =  H265Ebarrier3  user_id = 5 num_users = 10 user_ids = 0 1 2 3
[C66xx_6] 4 5 6 7 shmem name =  H265Ebarrier1  user_id = 6 num_users = 10 user_ids = 0 1 2 3 4 5 6 7 8 9 shmem name =  H265Ebarrier2  user_id = 6 num_users = 10 user_ids = 0 1 2 3 4 5 6 7 8 9 shmem name =  H265Ebarrier3  user_id = 6 num_users = 10 user_ids = 0 1 2 3
[C66xx_8] int13  user_id = 8 num_users = 2 user_ids = 8 9 shmem name =  barrier syncPoint15  user_id = 8 num_users = 2 user_ids = 8 9 shmem name =  barrier syncPoint17  user_id = 8 num_users = 2 user_ids = 8 9 shmem name =  H265Ebarrier1  user_id = 8 num_users = 10 
[C66xx_9] shmem name =  barrier syncPoint13  user_id = 9 num_users = 2 user_ids = 8 9 shmem name =  barrier syncPoint15  user_id = 9 num_users = 2 user_ids = 8 9 shmem name =  barrier syncPoint17  user_id = 9 num_users = 2 user_ids = 8 9 shmem name =  H265Ebarrier1 
[C66xx_0] arrier1  user_id = 0 num_users = 10 user_ids = 0 1 2 3 4 5 6 7 8 9 shmem name =  H265Ebarrier2  user_id = 0 num_users = 10 user_ids = 0 1 2 3 4 5 6 7 8 9 shmem name =  H265Ebarrier3  user_id = 0 num_users = 10 user_ids = 0 1 2 3 4 5 6 7 8 9 shmem name =  H
[C66xx_1]  4 5 6 7 8 9 shmem name =  H265Ebarrier8  user_id = 1 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265Ebarrier9  user_id = 1 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265Ebarrier10  user_id = 1 num_users = 8 user_ids = 0 1 2 3 4 5 
[C66xx_2]  4 5 6 7 8 9 shmem name =  H265Ebarrier8  user_id = 2 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265Ebarrier9  user_id = 2 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265Ebarrier10  user_id = 2 num_users = 8 user_ids = 0 1 2 3 4 5 
[C66xx_3]  4 5 6 7 8 9 shmem name =  H265Ebarrier8  user_id = 3 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265Ebarrier9  user_id = 3 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265Ebarrier10  user_id = 3 num_users = 8 user_ids = 0 1 2 3 4 5 
[C66xx_4]  4 5 6 7 8 9 shmem name =  H265Ebarrier8  user_id = 4 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265Ebarrier9  user_id = 4 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265Ebarrier10  user_id = 4 num_users = 8 user_ids = 0 1 2 3 4 5 
[C66xx_5]  4 5 6 7 8 9 shmem name =  H265Ebarrier8  user_id = 5 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265Ebarrier9  user_id = 5 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265Ebarrier10  user_id = 5 num_users = 8 user_ids = 0 1 2 3 4 5 
[C66xx_6]  4 5 6 7 8 9 shmem name =  H265Ebarrier8  user_id = 6 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265Ebarrier9  user_id = 6 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265Ebarrier10  user_id = 6 num_users = 8 user_ids = 0 1 2 3 4 5 
[C66xx_8] user_ids = 0 1 2 3 4 5 6 7 8 9 shmem name =  H265Ebarrier2  user_id = 8 num_users = 10 user_ids = 0 1 2 3 4 5 6 7 8 9 shmem name =  H265Ebarrier3  user_id = 8 num_users = 10 user_ids = 0 1 2 3 4 5 6 7 8 9 shmem name =  H265Ebarrier8  user_id = 8 num_users 
[C66xx_9]  user_id = 9 num_users = 10 user_ids = 0 1 2 3 4 5 6 7 8 9 shmem name =  H265Ebarrier2  user_id = 9 num_users = 10 user_ids = 0 1 2 3 4 5 6 7 8 9 shmem name =  H265Ebarrier3  user_id = 9 num_users = 10 user_ids = 0 1 2 3 4 5 6 7 8 9 shmem name =  H265Ebarr
[C66xx_0] 265Ebarrier8  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265Ebarrier9  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265Ebarrier10  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265Ebarri
[C66xx_8] = 2 user_ids = 8 9 shmem name =  H265Ebarrier9  user_id = 8 num_users = 2 user_ids = 8 9 shmem name =  H265Ebarrier10  user_id = 8 num_users = 2 user_ids = 8 9 shmem name =  H265Ebarrier11  user_id = 8 num_users = 2 user_ids = 8 9 shmem name =  H265E_lock1
[C66xx_9] ier8  user_id = 9 num_users = 2 user_ids = 8 9 shmem name =  H265Ebarrier9  user_id = 9 num_users = 2 user_ids = 8 9 shmem name =  H265Ebarrier10  user_id = 9 num_users = 2 user_ids = 8 9 shmem name =  H265Ebarrier11  user_id = 9 num_users = 2 user_ids = 8
[C66xx_0] er11  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265E_lock100  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265E_lock200  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  shared_mem_pcontext
[C66xx_8] 01  user_id = 8 num_users = 2 user_ids = 8 9 shmem name =  H265E_lock201  user_id = 8 num_users = 2 user_ids = 8 9 shmem name =  shared_mem_pcontext01  user_id = 8 num_users = 2 user_ids = 8 9 type == SL2 size == 12904 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == c008000 
[C66xx_0] 00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == SL2 size == 12904 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == c008000 
[C66xx_8] shmem name =  shared_mem_NAL_params01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 73038 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 91000600 
[C66xx_0] shmem name =  shared_mem_NAL_params00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == DDR_CACHED size == 73038 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 91000880 
[C66xx_8] shmem name =  shared_mem_DataSync_params01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 800 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 91012400 
[C66xx_0] shmem name =  shared_mem_DataSync_params00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == DDR_CACHED size == 800 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 91012680 
[C66xx_8] shmem name =  shared_mem_entry_points01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 374 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 91012780 
[C66xx_0] shmem name =  shared_mem_entry_points00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == DDR_CACHED size == 374 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 91012a80 
[C66xx_8] shmem name =  shared_NAL_info01  user_id = 8 num_users = 2 user_ids = 8 9 type == SL2 size == 3504 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == c00b280 
[C66xx_0] shmem name =  shared_NAL_info00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == SL2 size == 3504 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == c00b280 
[C66xx_8] shmem name =  shared_mem_bitoutInit01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 24 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 91012a00 
[C66xx_0] shmem name =  shared_mem_bitoutInit00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == DDR_CACHED size == 24 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 91012d00 
[C66xx_8] shmem name =  shared_mem_CABAC_Context01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 1600 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 91012a80 
[C66xx_0] shmem name =  shared_mem_CABAC_Context00  user_id = 0 num_users = 2 user_ids = 0 1 type == DDR_CACHED size == 1600 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 91012d80 
[C66xx_8] shmem name =  shared_mem_CABAC_Context01  user_id = 8 num_users = 2 user_ids = 8 9 key = 848544 shmem address loc_mem == 91012a80 
[C66xx_0] shmem name =  shared_mem_CABAC_Context00  user_id = 0 num_users = 2 user_ids = 0 1 key = 84a6f4 shmem address loc_mem == 91012d80 
[C66xx_8] shmem name =  shared_mem_bitout01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 24 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 91013180 
[C66xx_0] shmem name =  shared_mem_bitout00  user_id = 0 num_users = 2 user_ids = 0 1 type == DDR_CACHED size == 24 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 91013480 
[C66xx_8] shmem name =  shared_mem_bitout01  user_id = 8 num_users = 2 user_ids = 8 9 key = 848544 shmem address loc_mem == 91013180 
[C66xx_0] shmem name =  shared_mem_bitout00  user_id = 0 num_users = 2 user_ids = 0 1 key = 84a6f4 shmem address loc_mem == 91013480 
[C66xx_8] shmem name =  shared_mem_bitconsumed01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 48 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 91013200 
[C66xx_0] shmem name =  shared_mem_bitconsumed00  user_id = 0 num_users = 2 user_ids = 0 1 type == DDR_CACHED size == 48 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 91013500 
[C66xx_8] shmem name =  shared_mem_bitconsumed01  user_id = 8 num_users = 2 user_ids = 8 9 key = 848544 shmem address loc_mem == 91013200 
[C66xx_0] shmem name =  shared_mem_bitconsumed00  user_id = 0 num_users = 2 user_ids = 0 1 key = 84a6f4 shmem address loc_mem == 91013500 
[C66xx_8] shmem name =  shared_mem_CABAC_params01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 24 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 91013300 
[C66xx_0] shmem name =  shared_mem_CABAC_params00  user_id = 0 num_users = 2 user_ids = 0 1 type == DDR_CACHED size == 24 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 91013600 
[C66xx_8] shmem name =  shared_mem_CABAC_params01  user_id = 8 num_users = 2 user_ids = 8 9 key = 848544 shmem address loc_mem == 91013300 
[C66xx_0] shmem name =  shared_mem_CABAC_params00  user_id = 0 num_users = 2 user_ids = 0 1 key = 84a6f4 shmem address loc_mem == 91013600 
[C66xx_8] shmem name =  shared_mem_LCU_strs01  user_id = 8 num_users = 2 user_ids = 8 9 type == SL2 size == 552 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == c00c080 
[C66xx_0] shmem name =  shared_mem_LCU_strs00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == SL2 size == 552 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == c00c080 
[C66xx_8] shmem name =  shared_mem_MV_Buf_loc01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 94080 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 91013400 
[C66xx_0] shmem name =  shared_mem_MV_Buf_loc00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == DDR_CACHED size == 94080 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 91013780 
[C66xx_8] shmem name =  shared_mem_MV_Buf01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 37632 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 9102a400 
[C66xx_0] shmem name =  shared_mem_MV_Buf00  user_id = 0 num_users = 2 user_ids = 0 1 type == DDR_CACHED size == 37632 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 9102a780 
[C66xx_8] shmem name =  shared_mem_MV_Buf01  user_id = 8 num_users = 2 user_ids = 8 9 key = 848544 shmem address loc_mem == 9102a400 
[C66xx_0] shmem name =  shared_mem_MV_Buf00  user_id = 0 num_users = 2 user_ids = 0 1 key = 84a6f4 shmem address loc_mem == 9102a780 
[C66xx_8] shmem name =  shared_mem_const01  user_id = 8 num_users = 2 user_ids = 8 9 type == SL2 size == 17256 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == c00c300 
[C66xx_0] shmem name =  shared_mem_const00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == SL2 size == 17256 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == c00c300 
[C66xx_8] shmem name =  shared_mem_scan_tables01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 16512 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 91033800 
[C66xx_0] shmem name =  shared_mem_scan_tables00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == DDR_CACHED size == 16512 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 91033c00 
[C66xx_8] shmem name =  shared_mem_pic_mngmt_str01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 123896 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 91037900 
[C66xx_0] shmem name =  shared_mem_pic_mngmt_str00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == DDR_CACHED size == 123896 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 91037d80 
[C66xx_8] shmem name =  shared_ScalingList01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 44520 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 91055d80 
[C66xx_0] shmem name =  shared_ScalingList00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == DDR_CACHED size == 44520 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 91056200 
[C66xx_8] shmem name =  shared_QPOffsetROI01  user_id = 8 num_users = 2 user_ids = 8 9 type == SL2 size == 240 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == c010680 
[C66xx_0] shmem name =  shared_QPOffsetROI00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == SL2 size == 240 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == c010680 
[C66xx_8] shmem name =  shared_mem_trans_coeffs01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 2949120 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 91060c80 
[C66xx_0] shmem name =  shared_mem_trans_coeffs00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == DDR_CACHED size == 2949120 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 91061100 
[C66xx_8] shmem name =  shared_mem_tmp_bitstream01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 3670016 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 91330d00 
[C66xx_0] shmem name =  shared_mem_tmp_bitstream00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == DDR_CACHED size == 3670016 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 91331200 
[C66xx_8] shmem name =  shared_NAL_info_rmt01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_UNCACHED size == 3504 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 86000200 
[C66xx_0] shmem name =  shared_NAL_info_rmt00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == DDR_UNCACHED size == 3504 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 86000380 
[C66xx_8] shmem name =  shared_mem_bitstream01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 3670016 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 916b0e00 
[C66xx_0] shmem name =  shared_mem_bitstream00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == DDR_CACHED size == 3670016 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 916b1380 
[C66xx_8] shmem name =  shared_mem_SwappedStream01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 3670016 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 91a30e80 
[C66xx_0] shmem name =  shared_mem_SwappedStream00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == DDR_CACHED size == 3670016 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 91a31480 
[C66xx_8] shmem name =  shared_mem_chip2chip  user_id = 8 num_users = 2 user_ids = 0 8 type == RMT_UNCACHED_NO_LOC size == 816 alignment == 128 
[C66xx_8] shm address glob_mem == f2000680 key = 848544 shmem address loc_mem == f2000680 
[C66xx_0] shmem name =  shared_mem_chip2chip  user_id = 0 num_users = 2 user_ids = 0 8 key = 84a6f4 shmem address loc_mem == f2000680 
[C66xx_8] shmem name =  shared_recon_stitch_buf  user_id = 8 num_users = 2 user_ids = 0 8 type == RMT_UNCACHED_NO_LOC size == 674784 alignment == 128 
[C66xx_8] shm address glob_mem == f2000a80 key = 848544 shmem address loc_mem == f2000a80 
[C66xx_0] shmem name =  shared_recon_stitch_buf  user_id = 0 num_users = 2 user_ids = 0 8 key = 84a6f4 shmem address loc_mem == f2000a80 
[C66xx_8] shmem name =  shared_mem_LCU_hdr_loc01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 545280 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 91db0f80 
[C66xx_0] shmem name =  shared_mem_LCU_hdr_loc00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == DDR_CACHED size == 545280 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 91db1600 
[C66xx_8] shmem name =  shared_mem_LCU_hdr01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 218112 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 91e36200 
[C66xx_0] shmem name =  shared_mem_LCU_hdr00  user_id = 0 num_users = 2 user_ids = 0 1 type == DDR_CACHED size == 218112 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 91e36880 
[C66xx_8] shmem name =  shared_mem_LCU_hdr01  user_id = 8 num_users = 2 user_ids = 8 9 key = 848544 shmem address loc_mem == 91e36200 
[C66xx_0] shmem name =  shared_mem_LCU_hdr00  user_id = 0 num_users = 2 user_ids = 0 1 key = 84a6f4 shmem address loc_mem == 91e36880 
[C66xx_8] shmem name =  shared_mem_LCU_hdr_EP01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 109056 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 91e6b680 
[C66xx_0] shmem name =  shared_mem_LCU_hdr_EP00  user_id = 0 num_users = 2 user_ids = 0 1 type == DDR_CACHED size == 109056 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 91e6bd00 
[C66xx_8] shmem name =  shared_mem_LCU_hdr_EP01  user_id = 8 num_users = 2 user_ids = 8 9 key = 848544 shmem address loc_mem == 91e6b680 
[C66xx_0] shmem name =  shared_mem_LCU_hdr_EP00  user_id = 0 num_users = 2 user_ids = 0 1 key = 84a6f4 shmem address loc_mem == 91e6bd00 
[C66xx_8] shmem name =  shared_mem_LCU_hdr_WF2_loc01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 545280 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 91e86100 
[C66xx_0] shmem name =  shared_mem_LCU_hdr_WF2_loc00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == DDR_CACHED size == 545280 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 91e86800 
[C66xx_8] shmem name =  shared_mem_tH265_SAOStr_loc01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 4800 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 91f0b380 
[C66xx_0] shmem name =  shared_mem_tH265_SAOStr_loc00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == DDR_CACHED size == 4800 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 91f0bb00 
[C66xx_8] shmem name =  shared_mem_SAOStr01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 240 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 91f0c700 
[C66xx_0] shmem name =  shared_mem_SAOStr00  user_id = 0 num_users = 2 user_ids = 0 1 type == DDR_CACHED size == 240 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 91f0ce80 
[C66xx_8] shmem name =  shared_mem_SAOStr01  user_id = 8 num_users = 2 user_ids = 8 9 key = 848544 shmem address loc_mem == 91f0c700 
[C66xx_0] shmem name =  shared_mem_SAOStr00  user_id = 0 num_users = 2 user_ids = 0 1 key = 84a6f4 shmem address loc_mem == 91f0ce80 
[C66xx_8] shmem name =  shared_mem_CTU_activity01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 33400 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 91f0c880 
[C66xx_0] shmem name =  shared_mem_CTU_activity00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == DDR_CACHED size == 33400 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 91f0d000 
[C66xx_8] shmem name =  shared_mem_chip_activity01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 1056 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 91f14b80 
[C66xx_0] shmem name =  shared_mem_chip_activity00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == DDR_CACHED size == 1056 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 91f15300 
[C66xx_8] shmem name =  shared_mem_top_left_recon_loc01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 737280 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 91f15000 
[C66xx_0] shmem name =  shared_mem_top_left_recon_loc00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == DDR_CACHED size == 737280 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 91f15800 
[C66xx_8] shmem name =  shared_mem_dblkd_edge_pixels01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 122880 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 91fc9080 
[C66xx_0] shmem name =  shared_mem_dblkd_edge_pixels00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == DDR_CACHED size == 122880 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 91fc9900 
[C66xx_8] shmem name =  shared_mem_top_left_recon01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 268 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 91fe7100 
[C66xx_0] shmem name =  shared_mem_top_left_recon00  user_id = 0 num_users = 2 user_ids = 0 1 type == DDR_CACHED size == 268 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 91fe7980 
[C66xx_8] shmem name =  shared_mem_top_left_recon01  user_id = 8 num_users = 2 user_ids = 8 9 key = 848544 shmem address loc_mem == 91fe7100 
[C66xx_0] shmem name =  shared_mem_top_left_recon00  user_id = 0 num_users = 2 user_ids = 0 1 key = 84a6f4 shmem address loc_mem == 91fe7980 
[C66xx_8] shmem name =  shared_mem_slice_tile_no_buf01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 48760 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 91fe7280 
[C66xx_0] shmem name =  shared_mem_slice_tile_no_buf00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == DDR_CACHED size == 48760 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 91fe7b80 
[C66xx_8] shmem name =  shared_mem_RefPic_strs01  user_id = 8 num_users = 2 user_ids = 8 9 type == SL2 size == 424 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == c010780 
[C66xx_0] shmem name =  shared_mem_RefPic_strs00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == SL2 size == 424 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == c010780 
[C66xx_8] shmem name =  shared_mem_recon01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 11655360 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 91ff3200 
[C66xx_0] shmem name =  shared_mem_recon00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == DDR_CACHED size == 11655360 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 91ff3b00 
[C66xx_8] shmem name =  shared_mem_recon_shared01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 488448 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 92b10b80 
[C66xx_0] shmem name =  shared_mem_recon_shared00  user_id = 0 num_users = 2 user_ids = 0 1 type == DDR_CACHED size == 488448 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 92b11480 
[C66xx_8] shmem name =  shared_mem_recon_shared01  user_id = 8 num_users = 2 user_ids = 8 9 key = 848544 shmem address loc_mem == 92b10b80 
[C66xx_0] shmem name =  shared_mem_recon_shared00  user_id = 0 num_users = 2 user_ids = 0 1 key = 84a6f4 shmem address loc_mem == 92b11480 
[C66xx_8] shmem name =  shared_mem_dblk_shared01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 4608 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 92b88000 
[C66xx_0] shmem name =  shared_mem_dblk_shared00  user_id = 0 num_users = 2 user_ids = 0 1 type == DDR_CACHED size == 4608 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 92b88900 
[C66xx_8] shmem name =  shared_mem_dblk_shared01  user_id = 8 num_users = 2 user_ids = 8 9 key = 848544 shmem address loc_mem == 92b88000 
[C66xx_0] shmem name =  shared_mem_dblk_shared00  user_id = 0 num_users = 2 user_ids = 0 1 key = 84a6f4 shmem address loc_mem == 92b88900 
[C66xx_8] shmem name =  shared_mem_SAO_shared01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 36864 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 92b89280 
[C66xx_0] shmem name =  shared_mem_SAO_shared00  user_id = 0 num_users = 2 user_ids = 0 1 type == DDR_CACHED size == 36864 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 92b89b80 
[C66xx_8] shmem name =  shared_mem_SAO_shared01  user_id = 8 num_users = 2 user_ids = 8 9 key = 848544 shmem address loc_mem == 92b89280 
[C66xx_0] shmem name =  shared_mem_SAO_shared00  user_id = 0 num_users = 2 user_ids = 0 1 key = 84a6f4 shmem address loc_mem == 92b89b80 
[C66xx_8] shmem name =  shared_mem_local_str01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_UNCACHED size == 384 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 86001000 
[C66xx_0] shmem name =  shared_mem_local_str00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == DDR_UNCACHED size == 384 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 86001180 
[C66xx_8] shmem name =  EDMA_State_Struct01  user_id = 8 num_users = 2 user_ids = 8 9 type == SL2 size == 320 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == c010980 
[C66xx_0] shmem name =  EDMA_State_Struct00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == SL2 size == 320 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == c010980 
[C66xx_8] shmem name =  shared_mem_Mode_Decision01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 8785920 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 92b92380 
[C66xx_0] shmem name =  shared_mem_Mode_Decision00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == DDR_CACHED size == 8785920 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 92b92d80 
[C66xx_8] shmem name =  shared_mem_Mode_Decision_Inter01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 1523200 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 933f3400 
[C66xx_0] shmem name =  shared_mem_Mode_Decision_Inter00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == DDR_CACHED size == 1523200 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 933f3e80 
[C66xx_8] shmem name =  shared_mem_Mode_Decision_Cost01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 2176000 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 93567280 
[C66xx_0] shmem name =  shared_mem_Mode_Decision_Cost00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == DDR_CACHED size == 2176000 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 93567d80 
[C66xx_8] shmem name =  shared_mem_SFRC_State01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_UNCACHED size == 672 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 86001180 
[C66xx_0] shmem name =  shared_mem_SFRC_State00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == DDR_UNCACHED size == 672 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 86001300 
[C66xx_8] shmem name =  shared_mem_Pre_CABAC_Info01  user_id = 8 num_users = 2 user_ids = 8 9 type == DDR_CACHED size == 11859120 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == 9377a780 
[C66xx_0] shmem name =  shared_mem_Pre_CABAC_Info00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == DDR_CACHED size == 11859120 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == 9377b300 
[C66xx_8] shmem name =  shared_mem_STM01  user_id = 8 num_users = 2 user_ids = 8 9 type == RMT_UNCACHED_LOC_SL2 size == 5328 alignment == 128 
[C66xx_8] key = 848544 shmem address loc_mem == fd2a0000 
[C66xx_0] shmem name =  shared_mem_STM00  user_id = 0 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 type == RMT_UNCACHED_LOC_SL2 size == 5328 alignment == 128 
[C66xx_0] key = 84a6f4 shmem address loc_mem == fd2a0000 
[C66xx_1] 6 7 shmem name =  H265Ebarrier11  user_id = 1 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265E_lock100  user_id = 1 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265E_lock200  user_id = 1 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem
[C66xx_2] 6 7 shmem name =  H265Ebarrier11  user_id = 2 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265E_lock100  user_id = 2 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265E_lock200  user_id = 2 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem
[C66xx_3] 6 7 shmem name =  H265Ebarrier11  user_id = 3 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265E_lock100  user_id = 3 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265E_lock200  user_id = 3 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem
[C66xx_4] 6 7 shmem name =  H265Ebarrier11  user_id = 4 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265E_lock100  user_id = 4 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265E_lock200  user_id = 4 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem
[C66xx_5] 6 7 shmem name =  H265Ebarrier11  user_id = 5 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265E_lock100  user_id = 5 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265E_lock200  user_id = 5 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem
[C66xx_6] 6 7 shmem name =  H265Ebarrier11  user_id = 6 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265E_lock100  user_id = 6 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265E_lock200  user_id = 6 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem
[C66xx_7] 6 7 shmem name =  H265Ebarrier11  user_id = 7 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265E_lock100  user_id = 7 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem name =  H265E_lock200  user_id = 7 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 shmem
[C66xx_9]  9 shmem name =  H265E_lock101  user_id = 9 num_users = 2 user_ids = 8 9 shmem name =  H265E_lock201  user_id = 9 num_users = 2 user_ids = 8 9 shmem name =  shared_mem_pcontext01  user_id = 9 num_users = 2 user_ids = 8 9 key = 848544 shmem address loc_mem [C66xx_9] == c008000 
[C66xx_1]  name =  shared_mem_pcontext00  user_id = 1 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == c008000 
[C66xx_2]  name =  shared_mem_pcontext00  user_id = 2 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == c008000 
[C66xx_3]  name =  shared_mem_pcontext00  user_id = 3 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == c008000 
[C66xx_4]  name =  shared_mem_pcontext00  user_id = 4 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == c008000 
[C66xx_5]  name =  shared_mem_pcontext00  user_id = 5 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == c008000 
[C66xx_6]  name =  shared_mem_pcontext00  user_id = 6 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == c008000 
[C66xx_7]  name =  shared_mem_pcontext00  user_id = 7 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == c008000 
[C66xx_9] shmem name =  shared_mem_NAL_params01  user_id = 9 num_users = 2 user_ids = 8 9 key = 848544 shmem address loc_mem == 91000600 
[C66xx_1] shmem name =  shared_mem_NAL_params00  user_id = 1 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91000880 
[C66xx_2] shmem name =  shared_mem_NAL_params00  user_id = 2 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91000880 
[C66xx_3] shmem name =  shared_mem_NAL_params00  user_id = 3 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91000880 
[C66xx_4] shmem name =  shared_mem_NAL_params00  user_id = 4 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91000880 
[C66xx_5] shmem name =  shared_mem_NAL_params00  user_id = 5 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91000880 
[C66xx_6] shmem name =  shared_mem_NAL_params00  user_id = 6 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91000880 
[C66xx_7] shmem name =  shared_mem_NAL_params00  user_id = 7 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91000880 
[C66xx_9] shmem name =  shared_mem_entry_points01  user_id = 9 num_users = 2 user_ids = 8 9 key = 848544 shmem address loc_mem == 91012780 
[C66xx_1] shmem name =  shared_mem_entry_points00  user_id = 1 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91012a80 
[C66xx_2] shmem name =  shared_mem_entry_points00  user_id = 2 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91012a80 
[C66xx_3] shmem name =  shared_mem_entry_points00  user_id = 3 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91012a80 
[C66xx_4] shmem name =  shared_mem_entry_points00  user_id = 4 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91012a80 
[C66xx_5] shmem name =  shared_mem_entry_points00  user_id = 5 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91012a80 
[C66xx_6] shmem name =  shared_mem_entry_points00  user_id = 6 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91012a80 
[C66xx_7] shmem name =  shared_mem_entry_points00  user_id = 7 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91012a80 
[C66xx_9] shmem name =  shared_NAL_info01  user_id = 9 num_users = 2 user_ids = 8 9 key = 848544 shmem address loc_mem == c00b280 
[C66xx_1] shmem name =  shared_NAL_info00  user_id = 1 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == c00b280 
[C66xx_2] shmem name =  shared_NAL_info00  user_id = 2 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == c00b280 
[C66xx_3] shmem name =  shared_NAL_info00  user_id = 3 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == c00b280 
[C66xx_4] shmem name =  shared_NAL_info00  user_id = 4 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == c00b280 
[C66xx_5] shmem name =  shared_NAL_info00  user_id = 5 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == c00b280 
[C66xx_6] shmem name =  shared_NAL_info00  user_id = 6 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == c00b280 
[C66xx_7] shmem name =  shared_NAL_info00  user_id = 7 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == c00b280 
[C66xx_9] shmem name =  shared_mem_LCU_strs01  user_id = 9 num_users = 2 user_ids = 8 9 key = 848544 shmem address loc_mem == c00c080 
[C66xx_1] shmem name =  shared_mem_LCU_strs00  user_id = 1 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == c00c080 
[C66xx_2] shmem name =  shared_mem_LCU_strs00  user_id = 2 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == c00c080 
[C66xx_3] shmem name =  shared_mem_LCU_strs00  user_id = 3 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == c00c080 
[C66xx_4] shmem name =  shared_mem_LCU_strs00  user_id = 4 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == c00c080 
[C66xx_5] shmem name =  shared_mem_LCU_strs00  user_id = 5 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == c00c080 
[C66xx_6] shmem name =  shared_mem_LCU_strs00  user_id = 6 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == c00c080 
[C66xx_7] shmem name =  shared_mem_LCU_strs00  user_id = 7 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == c00c080 
[C66xx_9] shmem name =  shared_mem_pic_mngmt_str01  user_id = 9 num_users = 2 user_ids = 8 9 key = 848544 shmem address loc_mem == 91037900 
[C66xx_1] shmem name =  shared_mem_pic_mngmt_str00  user_id = 1 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91037d80 
[C66xx_2] shmem name =  shared_mem_pic_mngmt_str00  user_id = 2 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91037d80 
[C66xx_3] shmem name =  shared_mem_pic_mngmt_str00  user_id = 3 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91037d80 
[C66xx_4] shmem name =  shared_mem_pic_mngmt_str00  user_id = 4 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91037d80 
[C66xx_5] shmem name =  shared_mem_pic_mngmt_str00  user_id = 5 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91037d80 
[C66xx_6] shmem name =  shared_mem_pic_mngmt_str00  user_id = 6 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91037d80 
[C66xx_7] shmem name =  shared_mem_pic_mngmt_str00  user_id = 7 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91037d80 
[C66xx_9] shmem name =  shared_mem_SwappedStream01  user_id = 9 num_users = 2 user_ids = 8 9 key = 848544 shmem address loc_mem == 91a30e80 
[C66xx_1] shmem name =  shared_mem_SwappedStream00  user_id = 1 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91a31480 
[C66xx_2] shmem name =  shared_mem_SwappedStream00  user_id = 2 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91a31480 
[C66xx_3] shmem name =  shared_mem_SwappedStream00  user_id = 3 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91a31480 
[C66xx_4] shmem name =  shared_mem_SwappedStream00  user_id = 4 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91a31480 
[C66xx_5] shmem name =  shared_mem_SwappedStream00  user_id = 5 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91a31480 
[C66xx_6] shmem name =  shared_mem_SwappedStream00  user_id = 6 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91a31480 
[C66xx_7] shmem name =  shared_mem_SwappedStream00  user_id = 7 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91a31480 
[C66xx_9] shmem name =  shared_mem_tmp_bitstream01  user_id = 9 num_users = 2 user_ids = 8 9 key = 848544 shmem address loc_mem == 91330d00 
[C66xx_1] shmem name =  shared_mem_tmp_bitstream00  user_id = 1 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91331200 
[C66xx_2] shmem name =  shared_mem_tmp_bitstream00  user_id = 2 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91331200 
[C66xx_3] shmem name =  shared_mem_tmp_bitstream00  user_id = 3 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91331200 
[C66xx_4] shmem name =  shared_mem_tmp_bitstream00  user_id = 4 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91331200 
[C66xx_5] shmem name =  shared_mem_tmp_bitstream00  user_id = 5 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91331200 
[C66xx_6] shmem name =  shared_mem_tmp_bitstream00  user_id = 6 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91331200 
[C66xx_7] shmem name =  shared_mem_tmp_bitstream00  user_id = 7 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == 91331200 
[C66xx_9] shmem name =  EDMA_State_Struct01  user_id = 9 num_users = 2 user_ids = 8 9 key = 848544 shmem address loc_mem == c010980 
[C66xx_1] shmem name =  EDMA_State_Struct00  user_id = 1 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == c010980 
[C66xx_2] shmem name =  EDMA_State_Struct00  user_id = 2 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == c010980 
[C66xx_3] shmem name =  EDMA_State_Struct00  user_id = 3 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == c010980 
[C66xx_4] shmem name =  EDMA_State_Struct00  user_id = 4 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == c010980 
[C66xx_5] shmem name =  EDMA_State_Struct00  user_id = 5 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == c010980 
[C66xx_6] shmem name =  EDMA_State_Struct00  user_id = 6 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == c010980 
[C66xx_7] shmem name =  EDMA_State_Struct00  user_id = 7 num_users = 8 user_ids = 0 1 2 3 4 5 6 7 key = 848544 shmem address loc_mem == c010980 
[C66xx_0] shmem name =  H265Ebarrier4  user_id = 0 num_users = 2 user_ids = 0 8 shmem name =  H265Ebarrier5  user_id = 0 num_users = 2 user_ids = 0 8 shmem name =  H265Ebarrier6  user_id = 0 num_users = 2 user_ids = 0 8 shmem name =  H265Ebarrier7  user_id = 0 num_u[C66xx_8] shmem name =  H265Ebarrier4  user_id = 8 num_users = 2 user_ids = 0 8 shmem name =  H265Ebarrier5  user_id = 8 num_users = 2 user_ids = 0 8 shmem name =  H265Ebarrier6  user_id = 8 num_users = 2 user_ids = 0 8 shmem name =  H265Ebarrier7  user_id = 8 num_u[C66xx_8] sers = 2 user_ids = 0 8 
[C66xx_8] Algorithm Instance
[C66xx_8] Creation for the Module Id:H265VENC_TI Ver:01.00.00.44  Released by:DEV.HEVC.E.C6678.01.00.00.44 Built:Oct 30 2014 16:19:52 Completed 
[C66xx_8] handle is 89000000 
[C66xx_0] sers = 2 user_ids = 0 8 
[C66xx_1] 
[C66xx_2] 
[C66xx_3] 
[C66xx_4] 
[C66xx_5] 
[C66xx_6] 
[C66xx_7] 
[C66xx_9] 
[C66xx_0] Algorithm Instance
[C66xx_1] Algorithm Instance
[C66xx_2] Algorithm Instance
[C66xx_3] Algorithm Instance
[C66xx_4] Algorithm Instance
[C66xx_5] Algorithm Instance
[C66xx_6] Algorithm Instance
[C66xx_7] Algorithm Instance
[C66xx_9] Algorithm Instance
[C66xx_0] Creation for the Module Id:H265VENC_TI Ver:01.00.00.44  Released by:DEV.HEVC.E.C6678.01.00.00.44 Built:Oct 30 2014 16:19:52 Completed 
[C66xx_1] Creation for the Module Id:H265VENC_TI Ver:01.00.00.44  Released by:DEV.HEVC.E.C6678.01.00.00.44 Built:Oct 30 2014 16:19:52 Completed 
[C66xx_2] Creation for the Module Id:H265VENC_TI Ver:01.00.00.44  Released by:DEV.HEVC.E.C6678.01.00.00.44 Built:Oct 30 2014 16:19:52 Completed 
[C66xx_3] Creation for the Module Id:H265VENC_TI Ver:01.00.00.44  Released by:DEV.HEVC.E.C6678.01.00.00.44 Built:Oct 30 2014 16:19:52 Completed 
[C66xx_4] Creation for the Module Id:H265VENC_TI Ver:01.00.00.44  Released by:DEV.HEVC.E.C6678.01.00.00.44 Built:Oct 30 2014 16:19:52 Completed 
[C66xx_5] Creation for the Module Id:H265VENC_TI Ver:01.00.00.44  Released by:DEV.HEVC.E.C6678.01.00.00.44 Built:Oct 30 2014 16:19:52 Completed 
[C66xx_6] Creation for the Module Id:H265VENC_TI Ver:01.00.00.44  Released by:DEV.HEVC.E.C6678.01.00.00.44 Built:Oct 30 2014 16:19:52 Completed 
[C66xx_7] Creation for the Module Id:H265VENC_TI Ver:01.00.00.44  Released by:DEV.HEVC.E.C6678.01.00.00.44 Built:Oct 30 2014 16:19:52 Completed 
[C66xx_9] Creation for the Module Id:H265VENC_TI Ver:01.00.00.44  Released by:DEV.HEVC.E.C6678.01.00.00.44 Built:Oct 30 2014 16:19:52 Completed 
[C66xx_0] handle is 89000000 
[C66xx_1] handle is 8A000000 
[C66xx_2] handle is 8B000000 
[C66xx_3] handle is 8C000000 
[C66xx_4] handle is 8D000000 
[C66xx_5] handle is 8E000000 
[C66xx_6] handle is 8F000000 
[C66xx_7] handle is 90000000 
[C66xx_9] handle is 8A000000


    There are seem like some errors in the LOG which generate by ccs, but the shm mem address is right.

    I have attached the config for enabling tiles and try encoding on  multi chip by enabling tiles, but corruption stream still be found in the multichips encode.

    Thanks and Regards,
    JL, Wang

  • 0 in reply to JL, Wang
    Prodigy 100 points

    Hi, Palachandra M V

    [Question1],  If  the stream on chip1 independently (Single chip mode) was corruption stream, is two-thirds of the image should be correct at least ?

    [Question2], I instead the PCIe space by the way which the shared memory was mapped as the description I have posted previously, is it feasible ?

     

    Thanks and Regards,
    JL, Wang

  • 0 in reply to JL, Wang
    Expert 1230 points

    Hi JL, Wang

    Please find my reply inline,

    1. As per my understanding, In your setup, Host and Chip0 is connected through PCIe and chip0 and chip1 are connected through Hyperlink, if chip1 needs to access shared host memory it must access through chip0 only.
    2. [Question1], If the stream on chip1 independently (Single chip mode) was corruption stream, is two-thirds of the image should be correct at least ?
    If the stream is encoded on chip1 independently (Single chip mode), the entire stream should be properly encoded.
    3. [Question3], I instead the PCIe space by the way which the shared memory was mapped as the description I have posted previously, is it feasible ?
    It should be feasible, if data transfers are carried as per the understanding and considering this chip1 should be able to encode independently in single chip mode. For multichip encoding, single chip encoding on chip1 should be working.
    4. Since you are using 2 chips, is it possible for you try encoding using all the 16 cores.

    Thanks and Regards,
    Palachandra M V

  • 0 in reply to Palachandra Venkataraju
    Expert 1230 points

    Hi JL, Wang

    I have attached the document which give basic information regarding data transfer mechanism, interchip communication and shared memory regions used in our encoding module.

    Thanks and Regards,
    Palachandra M V

    Data.doc

  • 0 in reply to Palachandra Venkataraju
    Prodigy 100 points

    Hi Palachandra M V

    I have found why the steam corruption was appeared, it is as following:

    When the mem_attr = RMT_UNCACHED_NO_LOC, Data transfer fails because the encoder lib will activate the EDMA to transfer the intermediate data to the share memory. But I have not a PCIe memroy space for two of chips(C6678), and I used the MPAX and the hyperlink moudle to map a “dummy PCIe”  and It has been explained on my earlier posts. But the MPAX only valid for  the access for the CPU, and  it is invalid for EDMA transfer.  So I have a few of  questions:

    [ question 1 ] Can I make the two chips assigned different address, but indeed the same data was accessed?   By using the Hyperlink, we can do this.

    [ question 2 ] Can I use other on-chip resources to replace the PCIe memory space ? Was It supportted by the encoder library? 

  • 0 in reply to JL, Wang
    Prodigy 100 points

    Hi Palachandra M V

    I have found why the steam corruption was appeared, it is as following:

    When the mem_attr = RMT_UNCACHED_NO_LOC, Data transfer fails because the encoder lib will activate the EDMA to transfer the intermediate data to the share memory. But I have not a PCIe memroy space for two of chips(C6678), and I used the MPAX and the hyperlink moudle to map a “dummy PCIe”  and It has been explained on my earlier posts. But the MPAX only valid for  the access for the CPU, and  it is invalid for EDMA transfer.  So I have a few of  questions:

    [ question 1 ] Can I make the two chips assigned different address, but indeed the same data was accessed?   By using the Hyperlink, we can do this.

    [ question 2 ] Can I use other on-chip resources to replace the PCIe memory space ? Was It supportted by the encoder library?

    Thanks and Regards,
    Palachandra M V

  • 0 in reply to JL, Wang
    Expert 1230 points

    Hi Jialiang Wang,

    Please find my answer inline:

    [ question 1 ] Can I make the two chips assigned different address, but indeed the same data was accessed? By using the Hyperlink, we can do this.
    [Palachandra] : Same data can be accessed across two chip using Interchip Memory (Shared DDR)

    [ question 2 ] Can I use other on-chip resources to replace the PCIe memory space ? Was It supportted by the encoder library?
    [Palachandra] : As per my understanding on-chip resource refers to Interchip Memory (Shared DDR), In that scenario encoder (multichip) does not support replacement of PCIe memory space to Interchip memory.

    Thanks and Regards,
    Palachandra M V

  • 0 in reply to Palachandra Venkataraju
    TI__Mastermind 39080 points
    Hi Jialiang Wang,
    Our current HEVC encoder multichip design requires all chips can connect to host memory. Changing the encoder to only one chip accesssing host memory requires library modifications. Please contact your local TI FAE in order for us to understand your final use case, products and potential market.
    Thank you,Paula