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DDR3 problem

Dear all,

We opened the following post "e2e.ti.com/.../446572" few day ago.

We were going through the spreadsheets that you mentioned and we noticed that when we reduce  the page size to 512. Now, the DDR3 is more stable than when the page size is 2K. Regarding the datasheet of the  MT41J128M16 DDR3 chip the page size should be 2K.

Why the DDR3 is stable when reduse the page size?

Best regards

George

  • Hello George,

    I will check on this and get back to you.

    Regards,
    Senthil
  • George,

    The MT41J128M16 is a 2Gb SDRAM from Micron.  It is in the x16 topology and the datasheet does say it has a 2KB page size.  However, since it is x16, it only has 10 column bits (A[9:0]) so its column addressing is actually only 1KB.  The spreadsheet should be filled out for 1KB page size since that is the number of column addresses.  I do not believe the addressing would even work if you chose 2KB.  Them memory would have had functional regions a non-functional regions in an alternating pattern.  This might even be the 2KB block size that you reference.  Please select  a column size of 1KB for this SDRAM.

    I have no idea why selecting a page size of 512B makes it better.  In this case you are giving up half of your memory (i.e. not using column address A9).  The resulting memory will be functional and contiguous but only half the expected size.

    Tom

  • Hello Tom,
    Thank you for the explanation. Includes all the details that I need. I set the page to 1K, and seems to not face any problem.
    I follow the spreadsheets to fill the values . However when I shutdown the fan then the temperatures is increased and the DDR3 is not stable anymore (initialization phase ).
    Any hint about this?

    Best regards
    George
  • George,

    Thermal is a system problem.  All devices must be operated within their rated range.  Some state junction temperature and some state case temperature.  You have to ensure the temps are keep at the proper range.

    The C665x device is not the only heat generating chip.  The power supply chips, clock generation chips and SDRAM also generate heat.  Mutual heating will then cause temp rise more than expected.  JEDEC thermal numbers assume no mutual heating on a large, empty board.  You need to measure the case temperature of the C665x device without compromising its thermal dissipation path (i.e. such as drilling a hole or slot in the heat sink to contact the lid while maintaining proper mounting and contact.

    SDRAM can support a mode where the refresh rate is doubled for high temp operation.  You might want to try this.

    Tom

  • Hello,

    You referred to ASR and SRT. Regarding the TI document you can enable either ASR or SRT only when the PL_Mode is 1 . Is this correct?

    Best regards

    Georgre

  • George,

    No, ASR and SRT are related solely to Self Refresh mode which is not a default mode.  I am simply referring to the Extended Temperature Refresh Period.

    Tom