This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

McASP transmitter buffer underrun

Hi all

I am using custom board with c6747 dsp. It has independent receiver and transmitter clocks. To test my board I have wrote simple examples using register polling technique. The problem is buffer underrun in transmitter section just after successful transition of the one 32b word. Receiver part seems to be ok.

I am using  XDS100v2 USB emulator.

// main.c

...

// init peripheral by i2c

configure_mcasp();

while(1) {

push(111); // 111 just for example

}

// configuration code

...

// RX
mcaspRegs->RMASK = 0xffffffff; // No padding used
mcaspRegs->RFMT = 0x000080F8; // MSB 32bit, 0-delay, no pad, CFGBus
mcaspRegs->AFSRCTL = 0x00000110; // 2TDM, 1bit Rising, EXTERNAL FS, word
mcaspRegs->ACLKRCTL = 0x00000043; // Rising EXTERNAL CLK,1:1 with TX clock
mcaspRegs->AHCLKRCTL = 0x00000000; // EXTERNAL HCLK
mcaspRegs->RTDM = 0x00000003; // Slots 0,1
mcaspRegs->RINTCTL = 0x00000000; // Not used
mcaspRegs->RCLKCHK = 0x00FF0008; 

// TX - mine current
mcaspRegs->XMASK = 0xffffffff;
mcaspRegs->XFMT = 0x000080F8;
mcaspRegs->AFSXCTL = 0x00000112;
mcaspRegs->ACLKXCTL = 0x00000063;
mcaspRegs->AHCLKXCTL = 0x0000C001;
mcaspRegs->XTDM = 0x00000003;
mcaspRegs->XINTCTL = 0x00000000; // not used yet
mcaspRegs->XCLKCHK = 0x00FF0008;

mcaspRegs->SRCTL2 = 0x000E; // AXR[2] --> DIN MIC
mcaspRegs->SRCTL7 = 0x000D; // AXR[7] <-- DOUT

mcaspRegs->PFUNC = 0; // All MCASPs
mcaspRegs->PDIR = 0x1c000080;

...

// push code

System_printf("Push next 1\n");
static Uint32 XDATA_BIT = 0x20;
while ( (mcaspRegs->XSTAT & XDATA_BIT ) != XDATA_BIT) {
System_printf("XSTAT = %lx\n", mcaspRegs->XSTAT);
}
mcaspRegs->XBUF7 = value;
System_printf("Push next 2\n");

And finally log file looks like this

Push next 1
Push next 2
Push next 1
XSTAT = 151
XSTAT = 159
XSTAT = 151
XSTAT = 159
XSTAT = 151
...

Similar example with polling RSTAT works OK. 

So, what can be the reason of problem?

Thanks and regards.

  • I have the same problem. buffer underrun and XERR bits are set. Interestingly, for me, writing to XBUF works fine for polling. But if written in an interrupt, XBUF stores the value and fails to transmit on the AXR line. Are you clearing the XDATA bit after writing once? Writing a 1 to the bit will clear it
    mcaspRegs->XBUF7 = value;
    mcaspRegs-> XSTAT = 0x20;
  • >Are you clearing the XDATA bit after writing once?
    No, actually I dont. Should I?
    I am not clearing RDATA 0x20 too but receiving works well.
  • The problem seems to happen for TX only, See 2046.C6000 peripheral guide.pdf

    section 23.2.4.1.2 when TX serialiser comes out of reset during initialisation, XSTAT[XDATA] is set to 1. not writing to XBUFn causes underrun.

  • Thank you very much for your help.
    During McASP initialization I do clearing XSTAT and writing to XBUF, I just have skipped that part in my code snippet. In polling function I have tried both ways (clearing 0x20 from XSTAT and not) and nothing have changed.
    Problem still occurs.
  • Hi,

    I have suggestions for you are below and kindly valdate the same:

    1. Start the Rx. & Tx. clocks after enabling error interrupts for McASP like

    /* Enable error interrupts for McASP */

     McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DATAREADY  

                                             | MCASP_TX_CLKFAIL

                                             | MCASP_TX_SYNCERROR

                                             | MCASP_TX_UNDERRUN);

     McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DATAREADY  

                                             | MCASP_RX_CLKFAIL

                                             | MCASP_RX_SYNCERROR

                                             | MCASP_RX_OVERRUN);

    /* Start the clocks */

        McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);

        McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);

    2. Please ensure codec ISR mapping to CPU mask interrupt C674X_MASK_INTx should be done before configuring the AIC31 codec for I2S mode:

         IntRegister(C674X_MASK_INTx, Codec_ISR);

         IntEventMap(C674X_MASK_INTx, SYS_INT_MCASP0_INT);

         IntEnable(C674X_MASK_INTx);

    3.  In the McASPI2SConfigure(void) function code, activate the state machines after making sure that the XDATA bit is cleared to zero like below:

    /* make sure that the XDATA bit is cleared to zero */

    Kindly ensure to get INTx in the Interrupt vector table (i.e control is transferred to ISR - Codec_ISR() ).

    while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

    /* Activate the state machines */

     McASPRxEnable(SOC_MCASP_0_CTRL_REGS);

     McASPTxEnable(SOC_MCASP_0_CTRL_REGS);

    4. I think, to enable Tx. and Rx. McASP interrupts, kindly ensure to configure McASP error interrupts through  McASPTxIntEnable() & McASPRxIntEnable () which would trigger error interrupts if any.

     mcasp->rintctl    = 0x00000001;  // overrun interrupt only

     mcasp->xintctl    = 0x00000020;  // data interrupts

    Kindly validate the above configuration and try it.

    For more details to configure the transmitter and receiver interrupt control registers (XINTCTL & RINTCTL), kindly refer sections 26.3.20 & 26.3.32 in the OMAPL137 TRM below:

    http://www.ti.com/lit/ug/spruh92b/spruh92b.pdf

    Thanks & regards,

    Sivaraj K

    -------------------------------------------------------------------------------------------------------

    Please click the Verify Answer button on this post if it answers your question

    -------------------------------------------------------------------------------------------------------

  • Hi,

    As well, you could try the attached BSL test zip project in which you could test the AIC3106 McASP audio tone test code for OMAPL137

    After extracting the zip file, you see the .ccs project path for the above test example

    @ ~\ti\revg_EVMOMAPL137_BSL\evmomapl137_v1\dsp\tests\aic3106\aic3106

    as well, you could see the source files path @ ~\ti\revg_EVMOMAPL137_BSL\evmomapl137_v1\dsp\tests\aic3106

    /cfs-file/__key/communityserver-discussions-components-files/791/2311.6201.revg_5F00_EVMOMAPL137_5F00_BSL.zip

    Kindly validate your issue through trying the above test code for OMAPL137.

    Thanks & regards,

    Sivaraj K

    -------------------------------------------------------------------------------------------------------

    Please click the Verify Answer button on this post if it answers your question

    -------------------------------------------------------------------------------------------------------

  • Hi all!
    Seems like I found the Solution :)

    I just have got rid of all printfs and buffer underrun doesnot occur anymore!
  • thank you for posting it. Surprisingly, it stopped my underrun as well.