DSP 6670 Hibernate mode

Hari,

 1. So is hibernate mode the best option in my case ?

Yes. Your understanding is correct.

The KeyStone I device incorporates several hibernation modes that allow power consumption to be reduced during operation when only partial functionality is required (periods of inactivity). The benefits of using a hibernation mode include faster wake up times (as compared to cold boot) in addition to the typical power savings obtained.

 2. Is there a specific sequence I need to follow for putting the device in hibernate mode ?

No specific sequence is required. Access to the hibernation mode is obtained through writable registers. See the data manual for the memory map.

Thank you.

Raja,

1. When you say KeyStone I device incorporates several hibernation modes what hibernate modes are available other than Hibernate 1 and 2 ?
2. keystone device bootloader document has some sequence to power down the corepacs and hibernate mode which is not very clear to me.

e2e.ti.com/.../106842 has some sequence for Keystone 6678. This sequence does not seem to apply for 6670.

3. So I am wondering if there is a sequence I can follow to put 6670 in hibernate mode and get the DSPs out of hibernate mode ?

Thanks
Hari

Hi,

Is it required to hard/soft reset the device through software after the PWRSTATECTL register bits are written to enable hibernate mode ?

Thanks
Hari

1. We have only 2 modes.

2. You are referring to very good thread on this subject and thank you for pointing this out here. I will file an incident report to update the document with this information.

3. You can follow the same procedure to put the C6670 in hibernation mode as well. I think it should be common for keystone I devices.

Thank you.

Raja,

Thank you.  This is the sequence suggested for 6678 in the thread e2e.ti.com/.../106842

1. Power down domains of IPs that communicate with off chip masters (PCIe, SRIO, Hyperlink and Packet co-processor in that order)

     Note => Prior to powering down the above power domains, set  bits [15:12] of their respective PDCTL registers to 0000b. These bits are present in all PDCTL registers and will be documented in an updated version of the PSC user's guide.

2. Disable LPSCs for EMIF16 and TSIP0/1 (in that order)

3. Disable LPSC for debug_SS

4. Set bits [15:12] in PDCTL of Corepac 0-7 to 0000b

     Then power down Corepac 1-7 power domains (Leave CorePac0 power domain ON)

5. Configure DDR3 for hibernation: a) Set the RESETISO bit in MDCTL of DDR3 to enable reset isolation. b) Then put DDR3 in self refresh by programming LPMODE field in PMCTL register to 0x2 (Refer to DDR3 controller user's guide)

6. Program bits [15:12] of MSMC power domain to 0001b to put MSMC RAM in retention mode for hibernation 1 OR program them to 0000b (completely OFF, no retention) for hibernation 2 mode. Then power down MSMC power domain => This is the only step different for hiber 1 v/s hiber 2.

7. Configure all PLL controller reset inputs in RSCFG register as hard resets. You will have to unlock writes to RSCFG by first writing a key to RSTCTRL register (Refer to PLL controller users guide)

8. Program PWRSTATECTL to reflect appropriate power saving mode (hiber 1 or hiber 2)

9. Power down CorePac0 power domain

1. Few power domains(Step 2) are not present in 6670.

2. In step 6 why MSMC power domain is manually configured. Is this not configured by default when hibernate mode is selected?

3. In step 7 resets are configured as hard resets. Is there a reason for this ?

4. In the above referred thread it was mentioned  that power downing the corepac causes CCS to hang. Did someone verify this behavior?

5. Has anyone tried putting 6670 chip in hibernate mode ?

6. Is there any document on the hibernate power savings ?

This hibernate mode is a high priority for us. So I need some help in configuring this in right way for 6670 DSP.

Thanks

Hari

Hi,

I am really waiting on this . Hopefully someone is looking into this issue.

Thanks
Hari

Hi Hari,

Apologize for the delay. We will update you shortly on the above questions. Thank you for your patience.

Raja,

Checking in to see if there are any developments here.

Thanks,

Paul

Hi Aditya,

Thank you very much for looking into this issue. I have few questions in the time I get demo from you.

Hibernation mode exit is triggered only by hard reset. Hence configured that way. On exit, control will branch to the branch address programmed in the PWRSTATECTL register (bits 31-3).

1. The Bootloader document (SPRUGY5C- Section 2.2.3) says, When the hard or soft reset is triggered to exit from Hibernation2 mode, the MSMC is also reset. As per the document either hard or soft reset can trigger the hibernate mode exit. Does the document need to be updated with just hard reset ?

2. What exactly does the hibernate mode exit mean ?  How is it different from disabling the hibernation bit in PWRSTATECTL register ?(This register is cleared only by POR and will survive all other device resets - SPRS689D - 3.3.10 )

Thanks

Hari

Hi Aditya,

Any updates on the demo for 6670 hibernate mode ?

Thanks
Hari

Hi Hari,

Working on it. I'll have it by Monday. Sorry for the delay.

Hari,

Here you go. You can test out this hibernation2 demo on C6670 EVM. There is a readme with source code provided. You will need CCSv6 and C6670 PDK install for it to work. Let me know if you have any questions.

At a later stage, I plan to add a feature that prints a "wake up" message to UART console to make it better demonstrable. But this should be good to get you started with how to enter and exit hibernation. Let me know if you have any questions.

HibernationRecoverLE_6670.zip

Hi Aditya,

Thank you very much. It seems like working. These are the issues I noticed.

1. I cannot load the .out files if I don't initialize core 0 with gel file. My EVM is in SRIO boot mode. So do i need the gel file here ?
2. Any of the printf statements are not working. I don't see any output on the console. I have setup a break point before powering down core 0. Did you get the printfs working ?
3. And the make all command does not seem to work for me from the command prompt. So I created a new CCS project using the source files.


Thanks
Hari

Sorry, my e2e account was down so I could not log on.

Hari.. said:

1. I cannot load the .out files if I don't initialize core 0 with gel file. My EVM is in SRIO boot mode. So do i need the gel file here ?

The executable code (.text section) is placed in DDR3 memory so you will need to initialize DDR3 using GEL before loading the .out.

Hari.. said:

2. Any of the printf statements are not working. I don't see any output on the console. I have setup a break point before powering down core 0. Did you get the printfs working ?

I don't remember, and someone else is using my EVM right now. But I will get back tomorrow.

Hari.. said:

3. And the make all command does not seem to work for me from the command prompt. So I created a new CCS project using the source files.

Should be okay to create CCS project using the source files. I don't think "make" comes default with Windows. I downloaded GNU Win32 make package: 

The make file gets installed in C:\Program Files (x86)\GnuWin32\bin

Hi Aditya,

Thank you very much for your help. I am almost there in setting up the hibernate mode. I have few questions.

1. What would be different in configuring Hibernate mode 1 using MSMC ?

2. I am not using emulator on our custom board to run the same .out file on all the cores. I will use the boot loader to run the hibernate code. how can I run the hibernationInit code to power down cores 1, 2 and 3 ?


Thanks
Hari

Hari,

Hari.. said:

1. What would be different in configuring Hibernate mode 1 using MSMC ?

For hibernation 1, you can make the following changes:

sleep.cmd

1. Change .hibRecover > HIBR to .hibRecover > MSMCSRAM

main.c

1. Change HIBERNATION_RECOVER_ADDRESS to 0x0C000000
2. in enterHibernation(), remove the "| 0x6" in PWRSTATECTL write since 0 means hib1
3. Remove CSL_PSC_enableModuleResetIsolation(CSL_PSC_LPSC_EMIF4F); //no need since ddr3 can be allowed to reset in hib1
4. Remove steps to place MSMC in no-retention mode. We need MSMC SRAM in the default retention till access (RTA) mode since the critical information will be stored here
5. Instead, do *(unsigned int *)0x02620400 |= (1<<12); //set MSMC_BLOCK_PARITY_RST=1 in CHIP_MISC_CTL so the parity RAM will not reset during reset-initiated hibernation wake-up
6. Do not turn off MSMC power domain. Remove setDomainAndModulePower(CSL_PSC_LPSC_MSMCSRAM, CSL_PSC_PD_MSMCSRAM, 0);

Hari.. said:

2. I am not using emulator on our custom board to run the same .out file on all the cores. I will use the boot loader to run the hibernate code. how can I run the hibernationInit code to power down cores 1, 2 and 3 ?

Correct me if I misunderstood, but I think your concern about how to use the bootloader to run the same .out on multiple cores. I say same .out because the if statement in hibernationInit() ensures that cores 1-3 will power down. Please take a look at this thread for multicore boot (https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/449115). Let me know if you have any questions.

Hi Aditya,

Thank you. I will look at the multicore boot thread. A few more questions.

1. main.c
In step 3 do I need to enable reset isolation for MSMC ? CSL_PSC_enableModuleResetIsolation(CSL_PSC_LPSC_MSMCSRAM); or step 5 is doing the same ?

2. On EVM warm reset button is used to exit the hibernation mode. I am wondering how can I do this on my baseboard. Do I need to toggle the RESET pin for a hard reset(Table 7-9 SPRS689D) or is there any other way ? I don't think PLLCTL and emulation can be used for hardreset when the device is in hibernate mode with corepac shutdown.

Thanks
Hari

Hari,

Sorry for the wait.

Hari.. said:

In step 3 do I need to enable reset isolation for MSMC ? CSL_PSC_enableModuleResetIsolation(CSL_PSC_LPSC_MSMCSRAM); or step 5 is doing the same ?

You do not need to enable reset isolation for MSMC - it will retain the data in RAM through the reset operation. Step 5 preserves the parity RAM contents which are required for proper EDC operation.

Hari.. said:

Do I need to toggle the RESET pin for a hard reset(Table 7-9 SPRS689D) or is there any other way ?

Yes you should toggle the RESETz pin and follow the sequence documented in Section 7.4.2 Hard Reset SPRS689D:

The following sequence must be followed during a hard reset:

1. The RESET pin is pulled active low for a minimum of 24 CLKIN1 cycles. During this time the RESET signal is able to propagate to all modules (except those specifically mentioned above). All I/O are Hi-Z for modules affected by RESET, to prevent off-chip contention during the warm reset.

2. Once all logic is reset, RESETSTAT is driven active to denote that the device is in reset.

3. The RESET pin can now be released. A minimal device initialization begins to occur. Note that configuration pins are not re-latched and clocking is unaffected within the device.

4. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high).

Hi Aditya,

DDR3 hibernate mode worked fine on EVM. But on custom board toggling the reset line does not seem like exiting the hibernation mode. I don't see anything on serial console. I am still working on this.

I tried the MSMC hibernate mode as per your instructions on EVM. And I don't see it is working. Is there anything else need to be done for MSMC hibernate mode ? Bootloader document says MSMC config registers should be stored in shared memory. Is this required ?

And I see you are executing IDLE instruction after power downing the cores. Is there any reason for this ? How is this IDLE instruction executed after the core power down ?

For Core 0

setDomainAndModulePower(CSL_PSC_LPSC_GEM0, CSL_PSC_PD_GEM0, 0); //Core0 PD:13 PM:23

asm(" IDLE");

For Secondary cores

pdccmd = (volatile unsigned int*)CSL_CGEM0_5_POWER_DOWN_CONTROL_REGS;

*pdccmd |= CSL_CGEM_PDCCMD_GEMPD_MASK;

if(coreNum != MASTER_CORE){

/* Assembly code to put the core into an idle state */

asm(" IDLE");

Thanks

Hari