Other Parts Discussed in Thread: AM1808
Hi, I have questions about AM1808 pins and RESET. Q1. In AM1808 datasheet(sprs653e) page.58, there are following description for unused SATA_VDD. ////////////////////////////////////////////////////////////////////// Prior to silicon revision 2.0, this supply must be connected to a static 1.2V nominal supply. For silicon revision 2.0 and later, this supply may be left unconnected for additional power conservation. ////////////////////////////////////////////////////////////////////// My customer's AM1808 is rev2.1 and not using SATA. All SATA signal except SATA_VDD are configured as listed in "Table 3-31 Unused SATA Signal Configuration". They are connecting SATA_VDD to CVDD(1.3V) via 0 ohm resistor. Is there any problem connecting SATA_VDD to CVDD(1.3V) via "0 ohm" resistor? If there are problem, can you tell the details of problem? Q2. In AM1808 TRM(spruh82a) page.1573, there are following description for USB0_ID. ////////////////////////////////////////////////////////////////////// For OTG mode or device only mode of operation, do NOT connect the USB0_ID pin, that is, leave the pin floating ////////////////////////////////////////////////////////////////////// My customer are using USB0 as Device. But they are connecting USB0_ID to 3.3V via 10k ohm. By this connection, is there a possibility that a problem occurs? And they are requiring CPU internal circuit around USB_ID pin. Is it available? I guess internal circuit is not available to provide to the user. Q3. In AM1808 datasheet(sprs653e) page.58, there are following description for unused USB1_DP and USB1_DM. ////////////////////////////////////////////////////////////////////// VSS or No Connect ////////////////////////////////////////////////////////////////////// My customer are connecting USB1_DP and USB1_DM to GND via 0 ohm resistor. I understood that connecting to GND is okay, but is there a problem using 0 ohm resistor? Q4. OSCVSS pin are NC in my customer's board. Is it okay? If there are possibility that a problem occurs, please let me know the details. Q5. During RESET(K14 pin) assertion, if this reset signal flaps in High/Low, is there possibility that CPU malfunction? best regards, g.f.