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AM572x: Usage of PCIe

Kaka
Guru 24520 points
Other Parts Discussed in Thread: AM5728

Hi TI experts,

Please let me confirm the following question.
[Question.1]
My Customer would like to use the the 2-Lane PCIe.
And they would like to use them as one of two lanes use as RC and the other is EP
Can they use as this?

[Question.2]

If yes, would you please teach how they treat the CLK pin for PCIe?
They think that it need to input the same master clock to PCIe function block in order to be synchronized with them. But the clock pin is only for 1Lane.

If you have any questions, please let me know.
Best regards.
Kaka

  • 0
    TI__Guru**** 393215 points
    Hi,

    What software will they use?
  • 0 in reply to Biser Gatchev-XID
    Guru 24520 points
    Hi Biser,

    We do not have a answer for your question.
    It maybe Linux or RTOS like VxWorks.

    Best regards.
    Kaka
  • 0 in reply to Kaka
    TI__Guru**** 393215 points
    I will forward your question to the Linux team. We do not support VxWorks.
  • 0 in reply to Biser Gatchev-XID
    Guru 24520 points
    Hi Biser,

    Thank you for your response.
    In my understanding, my questions does not depends on the OS.
    It is the specification of device. Would you please re-confirm them?

    Best regards.
    Kaka
  • 0 in reply to Kaka
    TI__Guru 50170 points
    Hi, Kaka,
    We support 2-lane PCIe, but both in Root Complex mode. EndPonit mode is not supported.
    Rex
  • 0 in reply to Rex Chang
    Guru 24520 points
    Hi Rex,

    Thank you for your response.
    I checked the TRM for AM572x family, but it seems that the device on PCIe function supports the End point mode.
    I make extract the description about them from TRM.
    *************************
    • One PCIe (PCIe_SS1) operates as Gen-II 2-lanes supporting in either root-complex (RC) or end-point EP.
    • Two PCIe (PCIe_SS1 and PCIe_SS2) operates Gen-II 1-lane supporting either RC or EP with the possibility of one operating in Gen-I and one in Gen-II.
    *************************
    Would you please double check them?
    Best regards.
    Kaka
  • 0 in reply to Kaka
    TI__Guru 50170 points

    Hi, Kaka,

    The TRM shows what the hardware is capable of, but there is no PCI gadget framework that exists in Linux kernel to support EP mode. For our information if you don't mind, what will be the use case?

    Thanks!

    Rex

  • 0 in reply to Rex Chang
    TI__Guru 50170 points

    Kaka,

    I just run this with TI RTOS group, it has tested the EP mode on AM57x using Processor SDK 2.0. Due to the hardware constrain of the AM572x EVM, only 1-lane scenario was tested. The set up was between 2 EVMs, one as RC and the other as EP. This is not using Linux, but TI RTOS.

    Rex

  • 0 in reply to Rex Chang
    Guru 24520 points
    Hi Rex,

    Thank you for your comments.
    I could understand that AM572x supports the EP mode and RC mode. But would you please provide your answer for my first question?
    I would like to know whether customer will be able to use this 2-lane PCIe as one lane is set as RC mode and the other lane is set as EP mode at the same time.
    If yes, would you please teach me the way how customer handle/connect the CLK pin on this devies to the EP and RC PCIe devices?

    If you have any questions, please let me know.
    Best regards.
    Kaka
  • 0 in reply to Kaka
    Genius 3380 points
    Let me see if I can help clear this up.

    There are two PCIe controllers on the AM5728. If you configure the first controller as x2 lanes it must be EP or RC on both lanes since it is really the same PCIe instance and the second controller is not able to be used.

    If you configure each controller as x1 lane, you have two independent PCIe controllers and you can configure them as EP or RC, the same or differently if you want.

    As far as clocks go, the AM5728 is expecting a clock for the PCIe, this is common to both PCIe instances. This is just a reference clock for the PCIe. Since the clock does not come across the interface, it does not seem to matter if one instance is an RC and the other an EP as far as clocking is concerned. In our case we have one clock source, buffered three times, connected to the AM5728 and both devices connected to our x1 PCIe instances.
  • 0 in reply to Christopher Peters
    Guru 24520 points

    Hi Peters,

    Thank you for your kindly comments.
    I could understand that tre independent PCIe controllers can configure the EP or RC mode.
    I apologized for clocking, I am new to the field of PCIe. In my understanding, the RC instance should provide the clock source to EP instance. Is my understanding correct?

    If yes, AM572x only have one clock pin for one-PCIe controllers and it can configure as input and output pin. So if the two independent PCIe controllers mode is different(EP and RC), they cannot provide/input the clock source for each PCIe instances. This is why I would like to get TI's comments.
    Best regards.
    Kaka

  • 0 in reply to Kaka
    Guru 24520 points

    Hi Peters,

    Please let me confirm your comments for the clocking.

    I could not understand your answer for clocking in your previous post.  I made two slides which I understood from your provided comments.  

    Would you please check this?  And which  slide is near with your thinking?

    PCIe_AM572x.pptx

    If you have any questions, please let me know.

    Best regards.

    Kaka

  • 0 in reply to Kaka
    Genius 3380 points
    I think in picture A you intended to draw an arrow from the RC to the Clock Buffer. This is most definitely not the case, but I suppose it could be. Picture B is closer to the situation we are in, but only because our two EP's are on the same board as the AM5728 RC's. The line you have shown as X'ed out is actually an output from the 5728, which feeds the clock buffer, which in turn feeds back to the 5728 as the PCIe clock and also the two EP's.

    However, ignoring the pictures for a minute, I think the key point is that the "RC" does not provide the clock. Someone has to provide the clock, but as long as everyone gets it I don't think it matters who provides it. It is just a reference clock, the real PCIe clocks are generated inside the RC's and EP's.
  • 0 in reply to Christopher Peters
    TI__Guru* 95265 points
    Kaka,

    For PCIE operation, it is not necessary RC has to provide reference clock to EP. That is, RC and EP can operate on asynchronous clocks. As long as it has 100MHz reference clock received, it doesn't care whether it comes from on-board oscillator or from PCIE RC. Unless the RC is a ATX PC, which uses SSC to avoid EMI, then in this case EP has to use the clock from RC side.

    Regards, Eric