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OMAP-L138 Initialization functions for stand alone use

Todd Anderson78572
Guru 14640 points
Other Parts Discussed in Thread: OMAP-L138, OMAPL138

Reference:  https://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/131433

Present setup: LCDK138 board moving to custom target with OMAP-L138-EP.

 

The above reference shows a function that duplicates the actions of a CCS GEL file for PLL0.

I have not seen a STARTERWARE function that does similar. (We are not planning to use an RTOS on our particular application.)

Are there additional functions that need to be created for OMAP-L138 standalone applications?

For instance, what about PSC init, and PLL1 init? I see feedback on these from CCS.

Also, should the device_PLL0() function be run from ARM on bring-up? (I would assume yes.)

 

  • 0
    TI__Guru** 116100 points
    Dear Todd Anderson,
    If you use starterware package then you should use "bootloader" project (for standalone booting) which will take care the PLL initialization of both PLL controllers (ARM,DSP,DDR)

    Please refer to the starterware bootloader code:
    C:\ti\OMAPL138_StarterWare_1_10_04_01\bootloader\src\armv5\omapl138\bl_platform.c

    void BlPlatformConfig(void)
    {
    HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_SUSPSRC) &= SYSCFG_SUSPSRC_I2C0SRC |
    SYSCFG_SUSPSRC_UART2SRC |
    SYSCFG_SUSPSRC_SPI1SRC |
    SYSCFG_SUSPSRC_TIMER64P_0SRC;

    /* Set the PLL0 to generate 300MHz for ARM */
    PLL0Init(PLL_CLK_SRC, PLL0_MUL, PLL0_PREDIV, PLL0_POSTDIV,
    PLL0_DIV1,PLL0_DIV3, PLL0_DIV7);

    /* DDR Initialization */
    PLL1Init(PLL1_MUL, PLL1_POSTDIV, PLL1_DIV1,PLL1_DIV2, PLL1_DIV3);
    DDRInit();

    /* USB Initialization */
    USBSetup();

    /* Initializes the UART instance for serial communication. */
    UARTStdioInit();
    }

    Refer to this wiki page too.

    processors.wiki.ti.com/.../OMAPL138_StarterWare_Booting_And_Flashing
  • 0 in reply to Titusrathinaraj Stalin
    Guru 14640 points

    So, if I go through the setup for our target vs. setup for  LCDK138...

    I am also using the SYS_CLK_CALC_OMAP-L138_C674X_AM18X_v1p3.xls spreadsheet.

     

    PLL_CLK_SRC = 0     Does this represent CLKMODE?  I would assume 0 = OSCIN, in the case of LCDK138 = 24 MHz?

                               = 1       I would assume this is External Clock Source? (which is what we would have on the target board.)

    PLL0_MUL                     Would this be the same as PLLM?

    PLL0_PREDIV               Would this be the same as PREDIV?

    PLL0_POSTDIV             Would this be the same as POSTDIV?

    PLL0_DIV1                      not sure of this one...

    PLL0_DIV3                     PLLDIV3?

    PLL0_DIV7                     PLLDIV7?

  • 0 in reply to Todd Anderson78572
    TI__Mastermind 43660 points
    Todd,

    All your assumptions are correct. PLL0_DIV1 is the divider for SYSCLK1.

    Regards,
    Senthil