Hi,
I have questions about AM437x DPLL DDR.
Q1.
In AM437x TRM(spruhl7d) page.1327 Table 9-143,
there are clock signal cmd[2:0]_dfi_clk and data[3:0]_dfi_clk.
And it said these clock are clocked by the DDR PLL CLKOUT.
Is this mean that these clock signal are connected to DFI_CLK which is written at
page.282 "Figure 6-15 DDR PLL Structure" ?
Q2.
Also there are clock signal named "dll_clk" in page.1327 Table 9-143.
Is this "dll_clk" clock signal connected to "DLL clock" which is written at page.282 Figure 6-15 ?
Q3.
How to calculate DLL clock frequency?
I guess the formula for DLL clock is as follow:
DLL clock = DCOCLKLDO / M4
Is it correct?
If correct how to calculate the "DCOCLKLDO"?
Please tell me the formula for "DCOCLKLDO".
Q4.
In the following TI wiki, there are case that dll_clk need to be equal to DFI_CLK.
If DDR3 are running at 400MHz, DFI_CLK will be 400MHz.
But in TRM page.1327 Table 9-143, it said "dll_clk" maximum frequency is 350MHz.
I guess "dll_clk" maximum frequency should be 400MHz. Is this typo of TRM?
processors.wiki.ti.com/.../AM437x_DDR_Configuration_and_Programming_Guide PLL&tisearch=Search-EN
Q5.
There are "DPLL_REGM4XEN" bit in PRCM_CM_CLKMODE_DPLL_DDR register.
The description of this bit said "check the DPLL documentation to check when this mode can
be enabled. ". But I can't find the documentation.
In what case this "DPLL_REGM4XEN" should be enabled?
best regards,
g.f.
