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Memory mapping for A15

netrover
Intellectual 850 points

Has anyone seen problems assigning .text code to cache memory for OMAP5 type processors, such as the A15? Assigning cache memory to the C6x processor using the .cmd file works, while the A15 code does not run to completion and hits a branch to itself when that program is paused using Code Composer V5.4 in debug mode.

Thanks for any insight,

Dan

  • 0
    TI__Genius 12805 points

    I am not sure that I understand your question

    Do you mean that when you link your program, and the code resides in the .text section you wonder where to put it?

    The difference between the A15 and the DSP is that the DSP internal RAM can be SRAM (that is no cache) thus it has a global address. As you know caches in general do not have physical addresses, they are mirror of the actual address. In the C66 case the memory has actual address (but when you configure this memory as cache it mirrors the address of the cache line that is in the cache). The ARM A15 internal memory is only cache, cannot be configured as SRAM so it has no global address that anyone can access

    Do I understand your question?   Does the answer make sense?   If so, close the thread

    Ran

  • 0 in reply to ran35366
    Intellectual 850 points

    Ok, then the question is how do I access the A15 cache to try to speed up my A15 process? Or is the cache used automatically by the ARM processor?

    Mapping to the C6x cache shows a 5% improvement in processing speed so far, so I would want to try the same thing with the A15's cache.

    Thanks

  • 0 in reply to netrover
    TI__Genius 12805 points

    1. ARM cache - TI implementation of ARM is exactly the same as the standatd ARM A15,
    thus all collateral and functions that are offered by ARM will work for TI.
    2. In TI implementation the memory (MMU) is controlled by the device tree and the U-BOOT.
    I assume that the default is cache enabled.
    3. Just a reminder that the A15 has L1 cache for every core, L2 cache that is a unified cache
    for the case where there are multiple A15 cores.
    3. Depends on your algorithm I would expect better than 5% improvement in DSP performances
    with the cache.  It depends on how many times each value is read, and how much cache
    trashing happens.  I attach a few slides that describe how to optimize the DSP cache.

    /cfs-file/__key/communityserver-discussions-components-files/791/8512.Cache-Optimization.pptx

    Hope that it helps

    Ran

  • 0 in reply to ran35366
    Intellectual 850 points

    That looks like the answer. I am getting some ARM documentation at the ARM website. Will also checkout the DSP cache use information in the above Power Point file.

    Thanks!