This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Full leveling in C6657

Dear all, 

I have a question about full leveling procedure because it is a ambiguous description about registres configuration in document  sprugv8e.pdf and sprabl2d.pdf

In document sprugv8e.pdf 2.13.4, it is refered  in step 3  that "Program the write leveling initial values into the DATA0_PHY_WRLVL_INIT_RATIO to

DATA8_PHY_WRLVL_INIT_RATIO fields of the DDR3_CONFIG_2 to DDR3_CONFIG_10 registers
respectively. (See the tables in sections Section 4.33 to Section 4.41).
NOTE: The values to enter into the registers depend on the board topology and the DDR3 clock
frequency in use. The DDR3 clock frequency (half the data rate) and trace lengths for each
byte lane (CK-DQS pair) should be plugged in the appropriate fields in the accompanying
PHY calculation spreadsheet which generates the values to be programmed into the boot
config registers mentioned above.


Program the gate leveling initial values into the DATA0_PHY_GATELVL_RATIO to
DATA8_PHY_GATELVL_RATIO fields of the DDR3_CONFIG_14 to DDR3_CONFIG_22 registers
respectively. (See the tables in sections Section 4.43 to Section 4.51."

But in document  sprabl2d.pdf paragraph 3.3 refers that ".There must be no writes to any fixed ratio registers when full automatic leveling is used.". I am completely confused.   The DATAn_PHY_GATELVL_RATIO and  DDR3_CONFIG_GATELVL_RATIO are fixed ratio registers ,right?

The value of these values depends on the length of signals ,CLK and DATA.

We have done an implementation that configure the DDR3 in full auto leveling mode without set the aforementioned registers  and the DDR3 seems to be stable.We have done plenty of reboots in the system that use this configuration and we do not face any problem fro more that 4 months.

We indicate a problem in c6657 chip when we enable smartflex and the voltage of the core switch from 1.10 V to 0.95 V. We investigate further the full automatic leveling and we notice this difference. 

One more question : Could you please give us an example of a DDR3 register that we can read back to ensure that the full leveling finishes 

Best regards

George