Hi,
In my design i m using TMS320C6678 processor (@ 1.25 GHz) with DDR3-1066 .I m providing 100 MHz to DDR3 and core,PASS clk thro CDCM6208.I m getting PLL clock out for DDR3 1066 (533.33 MHz) when i am setting PLLM=15,PLLD=0 and output divide (in SEC_CTL register)=3. I m not getting sysclk1 as 1.25 GHz in any combination of PLLM,PLLD values (Nearest is PLLM=36 ,PLLD=0 Sysclk1=1233.33 or PLLM=37 ,PLLD=0 Sysclk1=1266.66 output divide =3 (which is set for DDR3) .My question is whether processor can take this sysclk1 value?
Regards,
Sivanantham
