AM572x questions

g.f.

Hi,

I have questions about AM572x.

Q1.There are three OPP mode(OPP_NOM, OPP_OD, OPP_HIGH).
Is it allow to disalbe the AVS and fix the OPP mode to OPP_NOM?

Q2.In AM572x EVM and IDK EVM schematics, DDR3L data bus layout seems wrong.
   For example, in AM572x EVM schematics(TI_AM572XEVM_REV_A3.pdf) page.21
   DDR1_D10(AM572x) are connected to DQ15(DDR3L Memory).
   Other DDR3 data bus connection seems wrong also.
   Is this typo of schematics?

Q3.In AM572x datasheet(sprs953) page.201 "Table 6-3 OSC0 Input Clock Electrical Characteristics",
   the description of Iin seems wrong.
   It said "Input current(3.3V mode)". I guess OSC0 Input current only support 1.8V.
   Is it typo of datasheet?

Q4.My customer are planning to use external oscillator for OSC0 and its output Rise/Fall Time(10% to 90%) Max 6ns.
Are there spec of AM572x OSC0 which prescribe Rise/Fall time of 10% to 90%?

best regards,
g.f.

over 9 years ago

0 Biser Gatchev-XID over 9 years ago

TI__Guru**** 393215 points

Hi,

1. See processors.wiki.ti.com/.../Linux_Core_Power_Management_User's_Guide_(v4.1) I would not advise disabling SmartReflex, as the OPP voltage is read from value programmed in device effuse.

2. There is no error in the schematics. DDR data bits can be swapped within the byte they belong to. They cannot be swapped across bytes. Exceptions are bits 0, 8, 16 and 24, which cannot be swapped as they are used for hardware leveling.

3. This is a typo.

4. Yes, see Table 6-4 in the AM572x Datasheet ES2.0.

0 g.f. over 9 years ago in reply to Biser Gatchev-XID

Guru 15520 points

Hi Biser,

Thank you for the reply and sorry for the delay.

I have additional questions.

1.I understood about AM572xEVM DDR3 schematics.
By the way do you know the reason why DDR3 data bits are swapped?

2.I understood that OSC rising/falling time are specified in AM572x datasheet Table 6-4.
What I want to know is, in which range the datasheet specified the rising/falling time(5ns).
Please take alook at attached file.

And I want to know if there are specified rising /falling time for range 10%-90%.
Because my customer are planning to use extenrnal oscillator and
its rising/falling time is 6ns(max) in range 10%-90%.

best regards,
g.f.

AM5728 OSC Rising_Falling Time.pptx

0 Biser Gatchev-XID over 9 years ago in reply to g.f.

TI__Guru**** 393215 points

1. To facilitate PCB routing.
2. See section 7.3.1.1 of the AM572x Datasheet SR2.0.

0 g.f. over 9 years ago in reply to Biser Gatchev-XID

Guru 15520 points

Hi Biser,

Thank you for the reply.
I uderstood.

best regards,
g.f.

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